Recent posts

#81

Trenz Electronic FPGA Modules / Re: TE0712_03

Last post by JH - November 26, 2024, 08:16:56 AM

Hi,
which reference CLK did you use for the CLK wizard IP? Does it match to the settings of your MMCM(CLK wizard)
ILA or VIO debug core are mostly not visible when the reference clk is not available.
br
John

#82

Trenz Electronic FPGA Modules / Re: Statement of volatility

Last post by JH - November 26, 2024, 08:05:16 AM

Hi,
TRM includes a list of storage devices, maybe this helps you:
https://wiki.trenz-electronic.de/display/PD/TE0720+TRM#TE0720TRM-InitialDeliveryState

You can identity used components from the list with the designator(IC in the TRM Table) in the schematic
https://shop.trenz-electronic.de/trenzdownloads/Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0720/REV04/Documents/SCH-TE0720-04-62I33MA.PDF

br
John

#83

Trenz Electronic FPGA Modules / Re: Oscillator on TE0720?

Last post by JH - November 26, 2024, 07:57:39 AM

Hi,
this module use 33.3MHz (SiT8008BI-73-XXS-33.333333E) for PS_CLK. See schematics page 11:
https://shop.trenz-electronic.de/trenzdownloads/Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0720/REV04/Documents/SCH-TE0720-04-62I33MA.PDF
br
John

#84

Trenz Electronic FPGA Modules / Issue with TE0720 module and t...

Last post by ritayandhara - November 22, 2024, 04:49:27 AM

Hi,
I have a carrier board from trenz which is TE0703-05 which im using with a xilinx fpga module ( TE0720 SoC) . Now when I go for the serial communication through any serial communicator like Putty or tera term , I cannot make a connection with the board. It keeps asking for some linux username and password. My main goal is to take the input from the user to do certain things with fpga eg. changing the frequency or may be blinking an led. But I cannot establish the connection. Any help will be  greatly appreciated. Thank You

#85

Trenz Electronic FPGA Modules / CR00103 Certus-NX LiteX suppor...

Last post by schaeferk - November 20, 2024, 02:06:04 PM

Hi,

The CR00103 Certus-NX development board ships with a pre-installed image that contains a VexRiscv-based SoC built with LiteX and Migen. As far as I know, the board is not officially supported by LiteX. Is it possible or planned to provide the necessary configuration files to build custom SoCs with LiteX for this board?

Kind regards,

Konstantin

#86

Trenz Electronic FPGA Modules / Re: Reflashing ZynqBerryZero

Last post by Sapmeister - November 20, 2024, 12:45:23 PM

Hi JH

I have the same problem with the same error message:

[Xicom 50-100] The current boot mode is QSPI.
If flash programming fails, configure device for JTAG boot mode and try again.

[Labtools 27-3161] Flash Programming Unsuccessful

Having read this thread it strikes a cord with me but I am new to this space.  Please can you clarify the below on how this is done to a beginner?

TE::pr_program_flash -swapp u-boot -def_fsbl

Is it the source .bin file or fsbl file that needs modifying?

Thanks

#87

Trenz Electronic FPGA Modules / Oscillator on TE0720?

Last post by AaronB - November 20, 2024, 03:27:24 AM

I'm trying to quantify the clock drift that the processor will undergo over time.  Can anyone identify what PS_CLK is used on the TE0720-04-62133MA or similar? I don't see this in the documentation, but if it's there, I apologize for missing it and I'd appreciate a pointer.

#88

Trenz Electronic FPGA Modules / Statement of volatility

Last post by AaronB - November 19, 2024, 06:07:44 PM

Is there any experience with getting a statement of volatility with a trenz 0720?  I'd like to find one if possible, for the "04-62133MA" variant or something close enough to match the storage components. 

Thanks
Aaron

#89

Trenz Electronic FPGA Modules / Problem with TLK106 on TEO712 ...

Last post by batte72 - November 18, 2024, 09:33:36 AM

 Good morning I have my udp Ip module that connect to TLK106 in RMII mode. I try to combine boostrap and BMCR bit autonegotiation in this manner:

I put High  at reset the PIN 17 and PIn 27 and after 200us I put pin17 in 'Z' and pin27  how input , then I sent with Typical MDC/MDIO Write Operation 4 sequence DEVICE_ADDR=00001  BMCR_ADDR = "00000"


    DATA_0      : std_logic_vector(15 downto 0) := "0001000000000000"; -- Dato 0
    DATA_1      : std_logic_vector(15 downto 0) := "0001001000000000"; -- Dato 1
    DATA_2      : std_logic_vector(15 downto 0) := "0001000000000000"; -- Dato 2
    DATA_3      : std_logic_vector(15 downto 0) := "0000000100000000"; -- Dato 3
    DATA_4      : std_logic_vector(15 downto 0) := "1000000000000000"; -- Dato 4

But when I send a test packet via PC the connection with ethernet in panel control is broken and TLK106 not run .I checked with ILA the clock 25MHz on MDC its ok !
Thanks

#90

Trenz Electronic FPGA Modules / Re: TE0701-06 Assembly Diagram...

Last post by milos.subotic@uns.ac.rs - November 15, 2024, 11:27:21 AM

Thank you.
I test it and it fit.