Recent posts

#1

Trenz Electronic FPGA Modules / TEB0911 Reference design gener...

Last post by Stonebull - January 21, 2025, 03:05:01 PM

Dear Trenz support team,
I'm trying to get the reference design 2019.2 for the TEB0911 to generate, using the script "_create_win_setup.cmd".

Although unfortunately, after the step of selecting the correct module (TEB0911-04-9BEX1MA) - the script aborts with the following error message:
ERROR: [TE_INIT-145] Script (TE::VIV::create_project) failed: ERROR: [Common 17-69] Command failed: Part 'xczu9eg-ffvb1156-1-e' not found

Also, I verified that indeed the board_files folder contains only two boards:

• TEB0911_9EG_1E
• TEB0911_15EG_1E

However, when trying to select a different module with matching name to the available board files, the script still failed with the same error message.

Can you please give me support on how to get started with the reference design for the TEB0911?

Best Regards

#2

Trenz Electronic FPGA Modules / How to setup CAN interface on ...

Last post by Bugtech - January 16, 2025, 04:38:25 PM

I am working on TE0818 board. I want to use CAN interface to send and receive data, Is there any guide or tutorial to setup this connection?

Are there any drivers needed to be installed separately? (CAN4Linux or SocketCAN)

I have petalinux 2022.2 in my board.

#3

Trenz Electronic FPGA Modules / Re: TEC0330: CVS List of SODIM...

Last post by JH - January 16, 2025, 10:07:13 AM

Hi,
you can download our 2021.2 reference design:
https://wiki.trenz-electronic.de/display/PD/TEC0330+Test+Board
https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/PCIe_Cards/TEC0330/Reference_Design/2021.2/test_board
Pin coordinates are included into the mig project file:
test_board\board_files\TEC0330\1.0\mig.prj

br
John

#4

UltraScale / Re: TE0818+TE0813 Block design...

Last post by M Kirberg - January 15, 2025, 02:50:51 PM

Provide a valid clock source to the referenced pin.

Alternatively deactivate the audio interface if not needed.

#5

Trenz Electronic FPGA Modules / Re: CYC5000 / TEI0050 Programm...

Last post by CaSchmidt - January 14, 2025, 09:30:05 PM

Hello,

I think, I have it working!

After consulting the schematic and the "Cyclone V Device Handbook",
I have changed the MSEL settings in the programming configuration to
"Active Serial x1"; contradicting the user guide.

Now I was able to program the QSPI!

Thank you, for the encouragement!

-- Carsten

#6

Trenz Electronic FPGA Modules / Re: CYC5000 / TEI0050 Programm...

Last post by Thomas D - January 13, 2025, 04:59:18 PM

Hi

FYI: I am using Quartus Prime 23.1 Lite Edition & Arrow USB Blaster 2.5.

Does this impact the flash programming procedure?

That should work. I have no problems with it.

br
Thomas

#7

Trenz Electronic FPGA Modules / TEC0330: CVS List of SODIMM204...

Last post by uwebonnes - January 13, 2025, 04:37:23 PM

To whom it may concern,

in the resources for TEC0330 I do not find a machine readable list of the connections from SODIMM204 socket to FPGA. Reading from the schematics is tedious and error prone. Please point me to such a list or provide it please if not yet available.

Best regards

#8

Trenz Electronic FPGA Modules / How to enable Ethernet in Peta...

Last post by r7 - January 12, 2025, 06:30:51 PM

Hello,

I'm trying to implement tftp booting for ZynqBerry TE0726-04-41C94-A. I successfully enabled Ethernet in linux kernel in Petalinux, but how to enable Ethernet in u-boot?
Here https://forum.trenz-electronic.de/index.php/topic,576.msg2556.html#msg2556 I read that you didn't try this. But it was 8 years ago. Any news on this?
Also I recompiled u-boot with these settings:

#define CONFIG_CMD_USB
#define CONFIG_USB_UHCI
#define CONFIG_USB_HOST_ETHER

but no Ethernet. After loading the kernel I have Ethernet.

#9

CYC1000 community projects / Re: I present a comunity of IN...

Last post by Subcritical - January 11, 2025, 11:21:51 AM

Writing the maximum Command Interpreter Path length , in MSX 1 From Fabio Benabeluto, and Radio-RK86 "РАДИО-86РК".

#10

MAX1000 community projects / Re: Playing ZX Spectrum in HDM...

Last post by Subcritical - January 10, 2025, 07:17:14 PM

This is the lines for using the DVI signal, the max 10 with a 55 nanometer achive the frecuencies of a DVI/Digital_video with no problem.

Code Select Expand

set_location_assignment PIN_H6 -to SYS_CLK
set_location_assignment PIN_H5 -to TMDS[0]
set_location_assignment PIN_K10 -to TMDS[1]
set_location_assignment PIN_H13 -to TMDS[2]
set_location_assignment PIN_J13 -to TMDS[3]
set_location_assignment PIN_K11 -to TMDS[4]
set_location_assignment PIN_K12 -to TMDS[5]
set_location_assignment PIN_J12 -to TMDS[6]
set_location_assignment PIN_L12 -to TMDS[7]

You can see the pin planner in the photo added.
It is a nice thing to have a 24 or 30 bit color scheme an consumes a very low count kles.
There is a screenshot also of the compiled piotr-go-vga, but consumes only 8 pins.
In order to reproduce a vga signal with 24bits.
You need:

8 Pins -> Red
8 Pins -> Green
8 Pins -> Blue
1 Pin -> Horizontal Sync
1 Pin -> Vertical Sync

This is the minimal signals you need in vga 8+8+8+1+1=26, but in a digital signal only uses 8 signals, the wrapper used could give 30bits but the implementation only gives 24bits, so 2 signals added for each RGB Color signals.
So for max1000 is more suitable a digital video signal.



You can see the impact in the utilization by entity of using a video signal compatible with DVI.