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#1
Trenz Electronic FPGA Modules / Re: Andromeda PHY not detected
Last post by CTSchorsch - November 07, 2025, 01:31:56 PMHi @akarcher,
can you go a little bit more in details how you fixed this issue ? I have a similiar problem with my phy addr
Thanks
Georg
can you go a little bit more in details how you fixed this issue ? I have a similiar problem with my phy addr
Thanks
Georg
#2
Trenz Electronic FPGA Modules / Re: PS->PL EMIO 1 GbE to SFP f...
Last post by paul - November 06, 2025, 08:15:17 PMFor those who might come across this thread later: the issue was the polarity of the MGT diffpair used for 1000BASE-X (MGT_TX3_P/N and MGT_RX3_P/N) is swapped between the TE0715-05 SOM and the TEBA0841 carrier card.
Enabling the transceiver control and status ports (see attached) and driving both gt0_txpolarity_in and gt0_rxpolarity_in high solved the problem for me.
Clock configuration was fine and handled properly by Trenz's code in FSBL.
Thank you John and Mohsen for your help!
Paul
Enabling the transceiver control and status ports (see attached) and driving both gt0_txpolarity_in and gt0_rxpolarity_in high solved the problem for me.
Clock configuration was fine and handled properly by Trenz's code in FSBL.
Thank you John and Mohsen for your help!
Paul
#3
Trenz Electronic FPGA Modules / Re: PS->PL EMIO 1 GbE to SFP f...
Last post by mch - November 05, 2025, 12:40:05 PMHi Paul,
Are you using our reference design?
https://wiki.trenz-electronic.de/display/PD/TE0715+Test+Board
https://www.trenz-electronic.de/Downloads/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0715/Reference_Design/2023.2/test_board
Which Vivado revision are you using?
We program the PLL chip (U10 SI5338) in our reference design using FSBL during booting via I2C interface. You can find the configuration core of the PLL in the FSBL source code in the "sw_lib" folder in our reference design folder.
The problem that the ethernet phy chip in your design cannot be found may be due to resetting. You should reset the ethernet phy chip in FSBL. The reset pin of the ethernet phy chip is connected to MIO50 in the hardware. You can use the AMD API commands in the FSBL code to reset the ethernet phy chip. If you are using our reference design, we did not reset the ethernet phy chip in FSBL code.
If you look in the "misc/si5338" folder, you will find the ClockBuilder project file for the PLL chip. We have selected IN3 with a frequency of 25MHz as the default input clock to generate a clock with a frequency of 125MHz.
Best regards,
Mohsen Chamanbaz
Are you using our reference design?
https://wiki.trenz-electronic.de/display/PD/TE0715+Test+Board
https://www.trenz-electronic.de/Downloads/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0715/Reference_Design/2023.2/test_board
Which Vivado revision are you using?
We program the PLL chip (U10 SI5338) in our reference design using FSBL during booting via I2C interface. You can find the configuration core of the PLL in the FSBL source code in the "sw_lib" folder in our reference design folder.
The problem that the ethernet phy chip in your design cannot be found may be due to resetting. You should reset the ethernet phy chip in FSBL. The reset pin of the ethernet phy chip is connected to MIO50 in the hardware. You can use the AMD API commands in the FSBL code to reset the ethernet phy chip. If you are using our reference design, we did not reset the ethernet phy chip in FSBL code.
If you look in the "misc/si5338" folder, you will find the ClockBuilder project file for the PLL chip. We have selected IN3 with a frequency of 25MHz as the default input clock to generate a clock with a frequency of 125MHz.
Best regards,
Mohsen Chamanbaz
#4
UltraScale / Re: TE0821 with TE0706 Carrier...
Last post by M Kirberg - November 05, 2025, 12:38:22 PMPlease look at the boot mode setting on the TE0821 CPLD. Setting S1:3 is not enough you need to be in JTAG mode thats what the error says, and you are most likely in QSPI mode.
PGOOD is used as additional bootmode pin in standard firmware, you need to "set" this signal also to the right value.
PGOOD is used as additional bootmode pin in standard firmware, you need to "set" this signal also to the right value.
#5
Trenz Electronic FPGA Modules / Re: Does TE0720 Ethernet work ...
Last post by viktornikolov - November 02, 2025, 01:21:52 PMQuote from: viktornikolov on October 28, 2025, 07:23:01 PMI don't know what's wrong with my MirkoTik switch.
There is nothing wrong with my switch. 😀
The lwIP works OK with the MikroTik switch. There is no issue with the ADC check forced by enabling the lwip220_lwip_dhcp_does_acd_check BSP option.
I was getting the "ERROR: DHCP request timed out" simply because the process of the switch offering an IP address to the Zynq board and the board doing the ACD check took more than 12 seconds. When I modified the code to extend the time limit to 16 seconds, everything worked fine.
It seems MirkoTik switches are not very fast at assigning an IP address via DHCP. The default RouterOS DHCP Server configuration includes conflict detection (the switch performs an ARP probe before assigning an IP address to a client).
#6
Trenz Electronic FPGA Modules / Re: Does TE0720 Ethernet work ...
Last post by viktornikolov - November 02, 2025, 01:19:15 PMQuote from: viktornikolov on October 28, 2025, 07:23:01 PMI still have no luck with a standalone app using the RAW lwIP API in Vitis 2025.1.
I made the standalone lwIP TCP Perf Client (RAW API) work in Vitis 2025.1. 🙂 The problem was in the timer configuration.
When you try to create the lwIP TCP Perf Client example in Vitis 2025.1, it tells you that you must set the BSP parameter XILTIMER_en_interval_timer to True. But that is wrong. This parameter can remain False. Instead, you must set the value of the parameter XILTIMER_tick_timer to one of the Zynq HW timers. (I will report this as a bug to AMD.)
With the tick_timer configured, the lwIP TCP Perf Client ran without issues. I achieved an average throughput of 831 Mbits/sec.
I added the project export to my GitHub.
The issue is that the main loop of the lwIP RAW API application relies on various counters to be updated every 50 ms. That is done in a function called by a timer interrupt.
The Vitis 2025.1 version of the code uses functions XTimer_SetInterval() and XTimer_SetHandler(). The initialization of the timer driver is done automatically and relies on the setting of the XILTIMER_tick_timer BSP parameter. Unfortunately, there is no proper error checking in the XTimer_* functions. They don't tell you that you are trying to call them on an uninitialized driver.
In Vitis 2024.2, the iperf client example uses the "old school" xscutimer.h API with explicit initialization and error checking. There is no dependency on BSP parameter settings.
#7
UltraScale / Re: TE0821 with TE0706 Carrier...
Last post by harrx - October 31, 2025, 03:15:46 PMQuote from: harrx on October 31, 2025, 03:13:18 PMDear,
Could you please help me resolve some the on-boarding issues with TE0821 module(2CG1E- 4 GB DDR) with TE0706 board.
I started with the Test board design v2024.2. I am stuck at the stage of the booting.
My config:
Power: 5V, 1A
Dip switches S1: (1:'1', 2:'0', 3:'0' 4:'1') Default
Reference design:
1. Booting with SD Card: I followed the reference design procedure and copied the 3 required files to the SD card Boot (1st) Partition. Nothing in the Root (2nd) partition. As soon as I power up the device with SD card inserted, all LEDs (incl. Ethernet) starts blinking and I see only? on the Serial terminal. Taking out the SD card, all LEDs are stable again.
2. QSPI Boot: TE::pr_program_flash -swapp u-boot ,, also does not work for me. I get the error "Flash programming is not supported in the selected boot mode". I tried switching S1-3:'1', but this does not help also.
3. Simple JTAG programming also does not work. Programming Baremetal application with Vitis also generates the error: "Flash programming is not supported in the selected boot mode, switch mode to JTAG".
Could you please help me resolve this issue. Point#03 is the most cirtical to be able to quickly load App changes from Vitis without the need to boot the whole device.
Best regards,
Haris.
#8
UltraScale / Re: TE0821 with TE0706 Carrier...
Last post by harrx - October 31, 2025, 03:14:30 PMQuote from: harrx on October 31, 2025, 03:13:18 PMDear,
Could you please help me resolve some the on-boarding issues with TE0821 module(2CG1E- 4 GB DDR) with TE0706 board.
I started with the Test board design v2024.2. I am stuck at the stage of the booting.
My config:
Power: 5V, 1A
Dip switches S1: (1:'1', 2:'0', 3:'0' 4:'1') Default
Reference design:
1. Booting with SD Card: I followed the reference design procedure and copied the 3 required files to the SD card Boot (1st) Partition. Nothing in the Root (2nd) partition. As soon as I power up the device with SD card inserted, all LEDs (incl. Ethernet) starts blinking and I see only "-?
2. QSPI Boot: TE::pr_program_flash -swapp u-boot ,, also does not work for me. I get the error "Flash programming is not supported in the selected boot mode". I tried switching S1-3:'1', but this does not help also.
3. Simple JTAG programming also does not work. Programming Baremetal application with Vitis also generates the error: "Flash programming is not supported in the selected boot mode, switch mode to JTAG".
Could you please help me resolve this issue. Point#03 is the most cirtical to be able to quickly load App changes from Vitis without the need to boot the whole device.
Best regards,
Haris.
#9
UltraScale / TE0821 with TE0706 Carrier Boa...
Last post by harrx - October 31, 2025, 03:13:18 PMDear,
Could you please help me resolve some the on-boarding issues with TE0821 module(2CG1E- 4 GB DDR) with TE0706 board.
I started with the Test board design v2024.2. I am stuck at the stage of the booting.
My config:
Power: 5V, 1A
Dip switches S1: (1:'1', 2:'0', 3:'0' 4:'1') Default
Reference design:
1. Booting with SD Card: I followed the reference design procedure and copied the 3 required files to the SD card Boot (1st) Partition. Nothing in the Root (2nd) partition. As soon as I power up the device with SD card inserted, all LEDs (incl. Ethernet) starts blinking and I see only "?" on the Serial terminal. Taking out the SD card, all LEDs are stable again.
2. QSPI Boot: TE::pr_program_flash -swapp u-boot ,, also does not work for me. I get the error "Flash programming is not supported in the selected boot mode". I tried switching S1-3:'1', but this does not help also.
3. Simple JTAG programming also does not work. Programming Baremetal application with Vitis also generates the error: "Flash programming is not supported in the selected boot mode, switch mode to JTAG".
Could you please help me resolve this issue. Point#03 is the most cirtical to be able to quickly load App changes from Vitis without the need to boot the whole device.
Best regards,
Haris.
Could you please help me resolve some the on-boarding issues with TE0821 module(2CG1E- 4 GB DDR) with TE0706 board.
I started with the Test board design v2024.2. I am stuck at the stage of the booting.
My config:
Power: 5V, 1A
Dip switches S1: (1:'1', 2:'0', 3:'0' 4:'1') Default
Reference design:
1. Booting with SD Card: I followed the reference design procedure and copied the 3 required files to the SD card Boot (1st) Partition. Nothing in the Root (2nd) partition. As soon as I power up the device with SD card inserted, all LEDs (incl. Ethernet) starts blinking and I see only "
?" on the Serial terminal. Taking out the SD card, all LEDs are stable again.2. QSPI Boot: TE::pr_program_flash -swapp u-boot ,, also does not work for me. I get the error "Flash programming is not supported in the selected boot mode". I tried switching S1-3:'1', but this does not help also.
3. Simple JTAG programming also does not work. Programming Baremetal application with Vitis also generates the error: "Flash programming is not supported in the selected boot mode, switch mode to JTAG".
Could you please help me resolve this issue. Point#03 is the most cirtical to be able to quickly load App changes from Vitis without the need to boot the whole device.
Best regards,
Haris.
#10
Arrow USB Programmer2 / Re: Step-by-step videos solvin...
Last post by Subcritical - October 31, 2025, 01:33:46 PM[Español]
En Linux, la mayor parte del tiempo está habilitado el propio controlador ftdi del nucleo del sistema operativo.
Por lo tanto,al principio, necesitas deshabilitar (incorporar a la lista negra) el módulo del kernel ftdi_sio de Linux.Esto también ocurre si el fptdi tiene un controlador proporcionado para las placas Xilinx, precisamente diseñado para los entornos de diseño FPGA ISE o Vivado.
Este es el mismo módulo del kernel que estoy usando con bastante éxito y extensivamente en mis otros proyectos FPGA.
Incorporar un controlador a la lista negra de este módulo del kernel impacta negativamente en otros trabajos que lo usen, es decir hay que siempre indicar que driver ftdi se usa, en el caso de max1000 o cyc1000 es el ft2232h con una configuración para la plataforma altera alvergada en la pequeña rom del ft2232h.
Biblioteca utilizada para trabajar con el formato de vectores svf:
https://github.com/ORSoC/libxsvf
Para instalar esta biblioteca, necesitas compilar el código fuente.
[English]
In linux most of the time is enabled the own ftdi driver.
So at first, you need to disable (blacklist) the linux ftdi_sio kernel
module.
This happens also if the fptdi has a driver provided to xilinx boards, that is for the ise or vivado fpga design suits.
This is the very same kernel module that I am using quite successfully and
extensively with my other FPGA projects. Blacklisting this kernel module will likely
impact my other work in a negative fashion.
Library used to play with vector format svf:
https://github.com/ORSoC/libxsvf
To install this library you need compile the source.
[Deutsh]
Unter Linux ist meistens der eigene FTDI-Treiber aktiviert.
Daher müssen Sie zunächst das Linux-Kernelmodul ftdi_sio deaktivieren (auf die schwarze Liste setzen).Dies passiert auch, wenn das FPTDI einen Treiber für Xilinx-Boards bereitstellt, der für die ISE- oder Vivado-FPGA-Design-Suiten gedacht ist.
Dies ist dasselbe Kernelmodul, das ich sehr erfolgreich und umfangreich bei meinen anderen FPGA-Projekten einsetze. Das Blacklisten dieses Kernelmoduls wird wahrscheinlich meine andere Arbeit negativ beeinflussen.Bibliothek, die für das Arbeiten mit dem Vektorformat SVF verwendet wird:
https://github.com/ORSoC/libxsvfUm
diese Bibliothek zu installieren, müssen Sie den Quellcode kompilieren.
En Linux, la mayor parte del tiempo está habilitado el propio controlador ftdi del nucleo del sistema operativo.
Por lo tanto,al principio, necesitas deshabilitar (incorporar a la lista negra) el módulo del kernel ftdi_sio de Linux.Esto también ocurre si el fptdi tiene un controlador proporcionado para las placas Xilinx, precisamente diseñado para los entornos de diseño FPGA ISE o Vivado.
Este es el mismo módulo del kernel que estoy usando con bastante éxito y extensivamente en mis otros proyectos FPGA.
Incorporar un controlador a la lista negra de este módulo del kernel impacta negativamente en otros trabajos que lo usen, es decir hay que siempre indicar que driver ftdi se usa, en el caso de max1000 o cyc1000 es el ft2232h con una configuración para la plataforma altera alvergada en la pequeña rom del ft2232h.
Biblioteca utilizada para trabajar con el formato de vectores svf:
https://github.com/ORSoC/libxsvf
Para instalar esta biblioteca, necesitas compilar el código fuente.
Code Select
make all[English]
In linux most of the time is enabled the own ftdi driver.
So at first, you need to disable (blacklist) the linux ftdi_sio kernel
module.
This happens also if the fptdi has a driver provided to xilinx boards, that is for the ise or vivado fpga design suits.
This is the very same kernel module that I am using quite successfully and
extensively with my other FPGA projects. Blacklisting this kernel module will likely
impact my other work in a negative fashion.
Library used to play with vector format svf:
https://github.com/ORSoC/libxsvf
To install this library you need compile the source.
Code Select
make all
[Deutsh]
Unter Linux ist meistens der eigene FTDI-Treiber aktiviert.
Daher müssen Sie zunächst das Linux-Kernelmodul ftdi_sio deaktivieren (auf die schwarze Liste setzen).Dies passiert auch, wenn das FPTDI einen Treiber für Xilinx-Boards bereitstellt, der für die ISE- oder Vivado-FPGA-Design-Suiten gedacht ist.
Dies ist dasselbe Kernelmodul, das ich sehr erfolgreich und umfangreich bei meinen anderen FPGA-Projekten einsetze. Das Blacklisten dieses Kernelmoduls wird wahrscheinlich meine andere Arbeit negativ beeinflussen.Bibliothek, die für das Arbeiten mit dem Vektorformat SVF verwendet wird:
https://github.com/ORSoC/libxsvfUm
diese Bibliothek zu installieren, müssen Sie den Quellcode kompilieren.
Code Select
make all