This design is targeted for xc7z010 board (part number: xc7z010clg225-1)

Zynq Design Summary

Device	xc7z010
SpeedGrade	-1
Part	xc7z010clg225-1
Description	Zynq PS Configuration Report with register details
Vendor	Xilinx

MIO Table View

MIO Pin	Peripheral	Signal	IO Type	Speed	Pullup	Direction
MIO 0	GPIO	gpio[0]	LVCMOS 3.3V	slow	enabled	inout
MIO 1	Quad SPI Flash	qspi0_ss_b	LVCMOS 3.3V	slow	enabled	out
MIO 2	Quad SPI Flash	qspi0_io[0]	LVCMOS 3.3V	slow	disabled	inout
MIO 3	Quad SPI Flash	qspi0_io[1]	LVCMOS 3.3V	slow	disabled	inout
MIO 4	Quad SPI Flash	qspi0_io[2]	LVCMOS 3.3V	slow	disabled	inout
MIO 5	Quad SPI Flash	qspi0_io[3]/HOLD_B	LVCMOS 3.3V	slow	disabled	inout
MIO 6	Quad SPI Flash	qspi0_sclk	LVCMOS 3.3V	slow	disabled	out
MIO 7	GPIO	gpio[7]	LVCMOS 3.3V	slow	disabled	out
MIO 8	GPIO	gpio[8]	LVCMOS 3.3V	slow	disabled	out
MIO 9	GPIO	gpio[9]	LVCMOS 3.3V	slow	enabled	inout
MIO 10	GPIO	gpio[10]	LVCMOS 3.3V	slow	enabled	inout
MIO 11	GPIO	gpio[11]	LVCMOS 3.3V	slow	enabled	inout
MIO 12	GPIO	gpio[12]	LVCMOS 3.3V	slow	enabled	inout
MIO 13	GPIO	gpio[13]	LVCMOS 3.3V	slow	enabled	inout
MIO 14	GPIO	gpio[14]	LVCMOS 3.3V	slow	enabled	inout
MIO 15	GPIO	gpio[15]	LVCMOS 3.3V	slow	enabled	inout
MIO 16	Unbonded	Unbonded
MIO 17	Unbonded	Unbonded
MIO 18	Unbonded	Unbonded
MIO 19	Unbonded	Unbonded
MIO 20	Unbonded	Unbonded
MIO 21	Unbonded	Unbonded
MIO 22	Unbonded	Unbonded
MIO 23	Unbonded	Unbonded
MIO 24	Unbonded	Unbonded
MIO 25	Unbonded	Unbonded
MIO 26	Unbonded	Unbonded
MIO 27	Unbonded	Unbonded
MIO 28	GPIO	gpio[28]	LVCMOS 3.3V	slow	enabled	inout
MIO 29	GPIO	gpio[29]	LVCMOS 3.3V	slow	enabled	inout
MIO 30	GPIO	gpio[30]	LVCMOS 3.3V	slow	enabled	inout
MIO 31	GPIO	gpio[31]	LVCMOS 3.3V	slow	enabled	inout
MIO 32	GPIO	gpio[32]	LVCMOS 3.3V	slow	enabled	inout
MIO 33	GPIO	gpio[33]	LVCMOS 3.3V	slow	enabled	inout
MIO 34	GPIO	gpio[34]	LVCMOS 3.3V	slow	enabled	inout
MIO 35	GPIO	gpio[35]	LVCMOS 3.3V	slow	enabled	inout
MIO 36	GPIO	gpio[36]	LVCMOS 3.3V	slow	enabled	inout
MIO 37	GPIO	gpio[37]	LVCMOS 3.3V	slow	enabled	inout
MIO 38	GPIO	gpio[38]	LVCMOS 3.3V	slow	enabled	inout
MIO 39	GPIO	gpio[39]	LVCMOS 3.3V	slow	enabled	inout
MIO 40	Unbonded	Unbonded
MIO 41	Unbonded	Unbonded
MIO 42	Unbonded	Unbonded
MIO 43	Unbonded	Unbonded
MIO 44	Unbonded	Unbonded
MIO 45	Unbonded	Unbonded
MIO 46	Unbonded	Unbonded
MIO 47	Unbonded	Unbonded
MIO 48	GPIO	gpio[48]	LVCMOS 3.3V	slow	enabled	inout
MIO 49	GPIO	gpio[49]	LVCMOS 3.3V	slow	enabled	inout
MIO 50	Unbonded	Unbonded
MIO 51	Unbonded	Unbonded
MIO 52	GPIO	gpio[52]	LVCMOS 3.3V	slow	enabled	inout
MIO 53	GPIO	gpio[53]	LVCMOS 3.3V	slow	enabled	inout

DDR Memory information

Parameter name	Value	Description
Enable DDR	0	Disable DDR

PS Clocks information

PS Reference Clock : 33.333333

Peripheral	PLL source	Frequency (MHz)
CPU 6x Freq (MHz)	ARM PLL	666.666687
QSPI Flash Freq (MHz)	IO PLL	200.000000
UART Freq (MHz)	IO PLL	100.000000
FPGA0 Freq (MHz)	IO PLL	50.000000
FPGA1 Freq (MHz)	IO PLL	10.000000
FPGA2 Freq (MHz)	IO PLL	10.000000
FPGA3 Freq (MHz)	IO PLL	10.000000

ps7_pll_init_data_3_0

Register Name	Address	Width	Type	Reset Value	Description
SLCR_UNLOCK	0XF8000008	32	WO	0x000000	SLCR Write Protection Unlock
ARM_PLL_CFG	0XF8000110	32	RW	0x000000	ARM PLL Configuration
ARM_PLL_CTRL	0XF8000100	32	RW	0x000000	ARM PLL Control
ARM_PLL_CTRL	0XF8000100	32	RW	0x000000	ARM PLL Control
ARM_PLL_CTRL	0XF8000100	32	RW	0x000000	ARM PLL Control
ARM_PLL_CTRL	0XF8000100	32	RW	0x000000	ARM PLL Control
ARM_PLL_CTRL	0XF8000100	32	RW	0x000000	ARM PLL Control
ARM_CLK_CTRL	0XF8000120	32	RW	0x000000	CPU Clock Control
DDR_PLL_CFG	0XF8000114	32	RW	0x000000	DDR PLL Configuration
DDR_PLL_CTRL	0XF8000104	32	RW	0x000000	DDR PLL Control
DDR_PLL_CTRL	0XF8000104	32	RW	0x000000	DDR PLL Control
DDR_PLL_CTRL	0XF8000104	32	RW	0x000000	DDR PLL Control
DDR_PLL_CTRL	0XF8000104	32	RW	0x000000	DDR PLL Control
DDR_PLL_CTRL	0XF8000104	32	RW	0x000000	DDR PLL Control
DDR_CLK_CTRL	0XF8000124	32	RW	0x000000	DDR Clock Control
IO_PLL_CFG	0XF8000118	32	RW	0x000000	IO PLL Configuration
IO_PLL_CTRL	0XF8000108	32	RW	0x000000	IO PLL Control
IO_PLL_CTRL	0XF8000108	32	RW	0x000000	IO PLL Control
IO_PLL_CTRL	0XF8000108	32	RW	0x000000	IO PLL Control
IO_PLL_CTRL	0XF8000108	32	RW	0x000000	IO PLL Control
IO_PLL_CTRL	0XF8000108	32	RW	0x000000	IO PLL Control
SLCR_LOCK	0XF8000004	32	WO	0x000000	SLCR Write Protection Lock

ps7_pll_init_data_3_0

SLCR SETTINGS

Register ( slcr )SLCR_UNLOCK

Register Name

Address

Width

Type

Reset Value

Description

Register Name	Address	Width	Type	Reset Value	Description
SLCR_UNLOCK	0XF8000008	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
UNLOCK_KEY	15:0	ffff	df0d	df0d	Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero.
SLCR_UNLOCK@0XF8000008	31:0	ffff		df0d	SLCR Write Protection Unlock

PLL SLCR REGISTERS

ARM PLL INIT

Register ( slcr )ARM_PLL_CFG

Register Name	Address	Width	Type	Reset Value	Description
ARM_PLL_CFG	0XF8000110	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_RES	7:4	f0	2	20	Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control
PLL_CP	11:8	f00	2	200	Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control
LOCK_CNT	21:12	3ff000	fa	fa000	Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before syaing locked.
ARM_PLL_CFG@0XF8000110	31:0	3ffff0		fa220	ARM PLL Configuration

UPDATE FB_DIV

Register ( slcr )ARM_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
ARM_PLL_CTRL	0XF8000100	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_FDIV	18:12	7f000	28	28000	Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL.
ARM_PLL_CTRL@0XF8000100	31:0	7f000		28000	ARM PLL Control

BY PASS PLL

Register ( slcr )ARM_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
ARM_PLL_CTRL	0XF8000100	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_BYPASS_FORCE	4:4	10	1	10	ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping.
ARM_PLL_CTRL@0XF8000100	31:0	10		10	ARM PLL Control

ASSERT RESET

Register ( slcr )ARM_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
ARM_PLL_CTRL	0XF8000100	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_RESET	0:0	1	1	1	PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)
ARM_PLL_CTRL@0XF8000100	31:0	1		1	ARM PLL Control

DEASSERT RESET

Register ( slcr )ARM_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
ARM_PLL_CTRL	0XF8000100	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_RESET	0:0	1	0	0	PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)
ARM_PLL_CTRL@0XF8000100	31:0	1		0	ARM PLL Control

CHECK PLL STATUS

Register ( slcr )PLL_STATUS

Register Name	Address	Width	Type	Reset Value	Description
PLL_STATUS	0XF800010C	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
ARM_PLL_LOCK	0:0	1	1	1	ARM PLL lock status: 0: not locked, 1: locked
PLL_STATUS@0XF800010C	31:0	1		1	tobe

REMOVE PLL BY PASS

Register ( slcr )ARM_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
ARM_PLL_CTRL	0XF8000100	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_BYPASS_FORCE	4:4	10	0	0	ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping.
ARM_PLL_CTRL@0XF8000100	31:0	10		0	ARM PLL Control

Register ( slcr )ARM_CLK_CTRL

Register Name	Address	Width	Type	Reset Value	Description
ARM_CLK_CTRL	0XF8000120	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
SRCSEL	5:4	30	0	0	Select the source used to generate the CPU clock: 0x: ARM PLL 10: DDR PLL 11: IO PLL This field is reset by POR only.
DIVISOR	13:8	3f00	2	200	Frequency divisor for the CPU clock source.
CPU_6OR4XCLKACT	24:24	1000000	1	1000000	CPU_6x4x Clock control: 0: disable, 1: enable
CPU_3OR2XCLKACT	25:25	2000000	1	2000000	CPU_3x2x Clock control: 0: disable, 1: enable
CPU_2XCLKACT	26:26	4000000	1	4000000	CPU_2x Clock control: 0: disable, 1: enable
CPU_1XCLKACT	27:27	8000000	1	8000000	CPU_1x Clock control: 0: disable, 1: enable
CPU_PERI_CLKACT	28:28	10000000	1	10000000	Clock active: 0: Clock is disabled 1: Clock is enabled
ARM_CLK_CTRL@0XF8000120	31:0	1f003f30		1f000200	CPU Clock Control

DDR PLL INIT

Register ( slcr )DDR_PLL_CFG

Register Name	Address	Width	Type	Reset Value	Description
DDR_PLL_CFG	0XF8000114	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_RES	7:4	f0	2	20	Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control.
PLL_CP	11:8	f00	2	200	Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control.
LOCK_CNT	21:12	3ff000	12c	12c000	Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked.
DDR_PLL_CFG@0XF8000114	31:0	3ffff0		12c220	DDR PLL Configuration

UPDATE FB_DIV

Register ( slcr )DDR_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
DDR_PLL_CTRL	0XF8000104	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_FDIV	18:12	7f000	20	20000	Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL.
DDR_PLL_CTRL@0XF8000104	31:0	7f000		20000	DDR PLL Control

BY PASS PLL

Register ( slcr )DDR_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
DDR_PLL_CTRL	0XF8000104	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_BYPASS_FORCE	4:4	10	1	10	DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping.
DDR_PLL_CTRL@0XF8000104	31:0	10		10	DDR PLL Control

ASSERT RESET

Register ( slcr )DDR_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
DDR_PLL_CTRL	0XF8000104	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_RESET	0:0	1	1	1	PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)
DDR_PLL_CTRL@0XF8000104	31:0	1		1	DDR PLL Control

DEASSERT RESET

Register ( slcr )DDR_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
DDR_PLL_CTRL	0XF8000104	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_RESET	0:0	1	0	0	PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)
DDR_PLL_CTRL@0XF8000104	31:0	1		0	DDR PLL Control

CHECK PLL STATUS

Register ( slcr )PLL_STATUS

Register Name	Address	Width	Type	Reset Value	Description
PLL_STATUS	0XF800010C	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
DDR_PLL_LOCK	1:1	2	1	2	DDR PLL lock status: 0: not locked, 1: locked
PLL_STATUS@0XF800010C	31:0	2		2	tobe

REMOVE PLL BY PASS

Register ( slcr )DDR_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
DDR_PLL_CTRL	0XF8000104	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_BYPASS_FORCE	4:4	10	0	0	DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping.
DDR_PLL_CTRL@0XF8000104	31:0	10		0	DDR PLL Control

Register ( slcr )DDR_CLK_CTRL

Register Name	Address	Width	Type	Reset Value	Description
DDR_CLK_CTRL	0XF8000124	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
DDR_3XCLKACT	0:0	1	1	1	DDR_3x Clock control: 0: disable, 1: enable
DDR_2XCLKACT	1:1	2	1	2	DDR_2x Clock control: 0: disable, 1: enable
DDR_3XCLK_DIVISOR	25:20	3f00000	2	200000	Frequency divisor for the ddr_3x clock
DDR_2XCLK_DIVISOR	31:26	fc000000	3	c000000	Frequency divisor for the ddr_2x clock
DDR_CLK_CTRL@0XF8000124	31:0	fff00003		c200003	DDR Clock Control

IO PLL INIT

Register ( slcr )IO_PLL_CFG

Register Name	Address	Width	Type	Reset Value	Description
IO_PLL_CFG	0XF8000118	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_RES	7:4	f0	4	40	Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control.
PLL_CP	11:8	f00	2	200	Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control.
LOCK_CNT	21:12	3ff000	fa	fa000	Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked.
IO_PLL_CFG@0XF8000118	31:0	3ffff0		fa240	IO PLL Configuration

UPDATE FB_DIV

Register ( slcr )IO_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
IO_PLL_CTRL	0XF8000108	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_FDIV	18:12	7f000	30	30000	Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for programming the PLL.
IO_PLL_CTRL@0XF8000108	31:0	7f000		30000	IO PLL Control

BY PASS PLL

Register ( slcr )IO_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
IO_PLL_CTRL	0XF8000108	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_BYPASS_FORCE	4:4	10	1	10	IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping.
IO_PLL_CTRL@0XF8000108	31:0	10		10	IO PLL Control

ASSERT RESET

Register ( slcr )IO_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
IO_PLL_CTRL	0XF8000108	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_RESET	0:0	1	1	1	PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)
IO_PLL_CTRL@0XF8000108	31:0	1		1	IO PLL Control

DEASSERT RESET

Register ( slcr )IO_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
IO_PLL_CTRL	0XF8000108	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_RESET	0:0	1	0	0	PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)
IO_PLL_CTRL@0XF8000108	31:0	1		0	IO PLL Control

CHECK PLL STATUS

Register ( slcr )PLL_STATUS

Register Name	Address	Width	Type	Reset Value	Description
PLL_STATUS	0XF800010C	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
IO_PLL_LOCK	2:2	4	1	4	IO PLL lock status: 0: not locked, 1: locked
PLL_STATUS@0XF800010C	31:0	4		4	tobe

REMOVE PLL BY PASS

Register ( slcr )IO_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
IO_PLL_CTRL	0XF8000108	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_BYPASS_FORCE	4:4	10	0	0	IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping.
IO_PLL_CTRL@0XF8000108	31:0	10		0	IO PLL Control

LOCK IT BACK

Register ( slcr )SLCR_LOCK

Register Name	Address	Width	Type	Reset Value	Description
SLCR_LOCK	0XF8000004	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
LOCK_KEY	15:0	ffff	767b	767b	Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero.
SLCR_LOCK@0XF8000004	31:0	ffff		767b	SLCR Write Protection Lock

ps7_clock_init_data_3_0

Register Name	Address	Width	Type	Reset Value	Description
SLCR_UNLOCK	0XF8000008	32	WO	0x000000	SLCR Write Protection Unlock
DCI_CLK_CTRL	0XF8000128	32	RW	0x000000	DCI clock control
LQSPI_CLK_CTRL	0XF800014C	32	RW	0x000000	Quad SPI Ref Clock Control
UART_CLK_CTRL	0XF8000154	32	RW	0x000000	UART Ref Clock Control
PCAP_CLK_CTRL	0XF8000168	32	RW	0x000000	PCAP Clock Control
FPGA0_CLK_CTRL	0XF8000170	32	RW	0x000000	PL Clock 0 Output control
CLK_621_TRUE	0XF80001C4	32	RW	0x000000	CPU Clock Ratio Mode select
APER_CLK_CTRL	0XF800012C	32	RW	0x000000	AMBA Peripheral Clock Control
SLCR_LOCK	0XF8000004	32	WO	0x000000	SLCR Write Protection Lock

ps7_clock_init_data_3_0

SLCR SETTINGS

Register ( slcr )SLCR_UNLOCK

Register Name

Address

Width

Type

Reset Value

Description

Register Name	Address	Width	Type	Reset Value	Description
SLCR_UNLOCK	0XF8000008	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
UNLOCK_KEY	15:0	ffff	df0d	df0d	Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero.
SLCR_UNLOCK@0XF8000008	31:0	ffff		df0d	SLCR Write Protection Unlock

CLOCK CONTROL SLCR REGISTERS

Register ( slcr )DCI_CLK_CTRL

Register Name	Address	Width	Type	Reset Value	Description
DCI_CLK_CTRL	0XF8000128	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
CLKACT	0:0	1	1	1	DCI clock control - 0: disable, 1: enable
DIVISOR0	13:8	3f00	f	f00	Provides the divisor used to divide the source clock to generate the required generated clock frequency.
DIVISOR1	25:20	3f00000	7	700000	Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider
DCI_CLK_CTRL@0XF8000128	31:0	3f03f01		700f01	DCI clock control

Register ( slcr )LQSPI_CLK_CTRL

Register Name	Address	Width	Type	Reset Value	Description
LQSPI_CLK_CTRL	0XF800014C	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
CLKACT	0:0	1	1	1	Quad SPI Controller Reference Clock control 0: disable, 1: enable
SRCSEL	5:4	30	0	0	Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL
DIVISOR	13:8	3f00	8	800	Divisor for Quad SPI Controller source clock.
LQSPI_CLK_CTRL@0XF800014C	31:0	3f31		801	Quad SPI Ref Clock Control

Register ( slcr )UART_CLK_CTRL

Register Name	Address	Width	Type	Reset Value	Description
UART_CLK_CTRL	0XF8000154	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
CLKACT0	0:0	1	1	1	UART 0 Reference clock control. 0: disable, 1: enable
CLKACT1	1:1	2	0	0	UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled
SRCSEL	5:4	30	0	0	Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL
DIVISOR	13:8	3f00	10	1000	Divisor for UART Controller source clock.
UART_CLK_CTRL@0XF8000154	31:0	3f33		1001	UART Ref Clock Control

TRACE CLOCK

Register ( slcr )PCAP_CLK_CTRL

Register Name	Address	Width	Type	Reset Value	Description
PCAP_CLK_CTRL	0XF8000168	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
CLKACT	0:0	1	1	1	Clock active: 0: Clock is disabled 1: Clock is enabled
SRCSEL	5:4	30	0	0	Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.
DIVISOR	13:8	3f00	8	800	Provides the divisor used to divide the source clock to generate the required generated clock frequency.
PCAP_CLK_CTRL@0XF8000168	31:0	3f31		801	PCAP Clock Control

Register ( slcr )FPGA0_CLK_CTRL

Register Name	Address	Width	Type	Reset Value	Description
FPGA0_CLK_CTRL	0XF8000170	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
SRCSEL	5:4	30	0	0	Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.
DIVISOR0	13:8	3f00	8	800	Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider.
DIVISOR1	25:20	3f00000	4	400000	Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide
FPGA0_CLK_CTRL@0XF8000170	31:0	3f03f30		400800	PL Clock 0 Output control

Register ( slcr )CLK_621_TRUE

Register Name	Address	Width	Type	Reset Value	Description
CLK_621_TRUE	0XF80001C4	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
CLK_621_TRUE	0:0	1	1	1	Select the CPU clock ratio: (When this register changes, no access are allowed to OCM.) 0: 4:2:1 1: 6:2:1
CLK_621_TRUE@0XF80001C4	31:0	1		1	CPU Clock Ratio Mode select

Register ( slcr )APER_CLK_CTRL

Register Name	Address	Width	Type	Reset Value	Description
APER_CLK_CTRL	0XF800012C	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
DMA_CPU_2XCLKACT	0:0	1	1	1	DMA controller AMBA Clock control 0: disable, 1: enable
USB0_CPU_1XCLKACT	2:2	4	1	4	USB controller 0 AMBA Clock control 0: disable, 1: enable
USB1_CPU_1XCLKACT	3:3	8	1	8	USB controller 1 AMBA Clock control 0: disable, 1: enable
GEM0_CPU_1XCLKACT	6:6	40	0	0	Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable
GEM1_CPU_1XCLKACT	7:7	80	0	0	Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable
SDI0_CPU_1XCLKACT	10:10	400	0	0	SDIO controller 0 AMBA Clock 0: disable, 1: enable
SDI1_CPU_1XCLKACT	11:11	800	0	0	SDIO controller 1 AMBA Clock control 0: disable, 1: enable
SPI0_CPU_1XCLKACT	14:14	4000	0	0	SPI 0 AMBA Clock control 0: disable, 1: enable
SPI1_CPU_1XCLKACT	15:15	8000	0	0	SPI 1 AMBA Clock control 0: disable, 1: enable
CAN0_CPU_1XCLKACT	16:16	10000	0	0	CAN 0 AMBA Clock control 0: disable, 1: enable
CAN1_CPU_1XCLKACT	17:17	20000	0	0	CAN 1 AMBA Clock control 0: disable, 1: enable
I2C0_CPU_1XCLKACT	18:18	40000	1	40000	I2C 0 AMBA Clock control 0: disable, 1: enable
I2C1_CPU_1XCLKACT	19:19	80000	1	80000	I2C 1 AMBA Clock control 0: disable, 1: enable
UART0_CPU_1XCLKACT	20:20	100000	1	100000	UART 0 AMBA Clock control 0: disable, 1: enable
UART1_CPU_1XCLKACT	21:21	200000	0	0	UART 1 AMBA Clock control 0: disable, 1: enable
GPIO_CPU_1XCLKACT	22:22	400000	1	400000	GPIO AMBA Clock control 0: disable, 1: enable
LQSPI_CPU_1XCLKACT	23:23	800000	1	800000	Quad SPI AMBA Clock control 0: disable, 1: enable
SMC_CPU_1XCLKACT	24:24	1000000	1	1000000	SMC AMBA Clock control 0: disable, 1: enable
APER_CLK_CTRL@0XF800012C	31:0	1ffcccd		1dc000d	AMBA Peripheral Clock Control

THIS SHOULD BE BLANK

LOCK IT BACK

Register ( slcr )SLCR_LOCK

Register Name	Address	Width	Type	Reset Value	Description
SLCR_LOCK	0XF8000004	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
LOCK_KEY	15:0	ffff	767b	767b	Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero.
SLCR_LOCK@0XF8000004	31:0	ffff		767b	SLCR Write Protection Lock

ps7_mio_init_data_3_0

Register Name	Address	Width	Type	Reset Value	Description
SLCR_UNLOCK	0XF8000008	32	WO	0x000000	SLCR Write Protection Unlock
MIO_PIN_00	0XF8000700	32	RW	0x000000	MIO Pin 0 Control
MIO_PIN_01	0XF8000704	32	RW	0x000000	MIO Pin 1 Control
MIO_PIN_02	0XF8000708	32	RW	0x000000	MIO Pin 2 Control
MIO_PIN_03	0XF800070C	32	RW	0x000000	MIO Pin 3 Control
MIO_PIN_04	0XF8000710	32	RW	0x000000	MIO Pin 4 Control
MIO_PIN_05	0XF8000714	32	RW	0x000000	MIO Pin 5 Control
MIO_PIN_06	0XF8000718	32	RW	0x000000	MIO Pin 6 Control
MIO_PIN_07	0XF800071C	32	RW	0x000000	MIO Pin 7 Control
MIO_PIN_08	0XF8000720	32	RW	0x000000	MIO Pin 8 Control
MIO_PIN_09	0XF8000724	32	RW	0x000000	MIO Pin 9 Control
MIO_PIN_10	0XF8000728	32	RW	0x000000	MIO Pin 10 Control
MIO_PIN_11	0XF800072C	32	RW	0x000000	MIO Pin 11 Control
MIO_PIN_12	0XF8000730	32	RW	0x000000	MIO Pin 12 Control
MIO_PIN_13	0XF8000734	32	RW	0x000000	MIO Pin 13 Control
MIO_PIN_14	0XF8000738	32	RW	0x000000	MIO Pin 14 Control
MIO_PIN_15	0XF800073C	32	RW	0x000000	MIO Pin 15 Control
MIO_PIN_28	0XF8000770	32	RW	0x000000	MIO Pin 28 Control
MIO_PIN_29	0XF8000774	32	RW	0x000000	MIO Pin 29 Control
MIO_PIN_30	0XF8000778	32	RW	0x000000	MIO Pin 30 Control
MIO_PIN_31	0XF800077C	32	RW	0x000000	MIO Pin 31 Control
MIO_PIN_32	0XF8000780	32	RW	0x000000	MIO Pin 32 Control
MIO_PIN_33	0XF8000784	32	RW	0x000000	MIO Pin 33 Control
MIO_PIN_34	0XF8000788	32	RW	0x000000	MIO Pin 34 Control
MIO_PIN_35	0XF800078C	32	RW	0x000000	MIO Pin 35 Control
MIO_PIN_36	0XF8000790	32	RW	0x000000	MIO Pin 36 Control
MIO_PIN_37	0XF8000794	32	RW	0x000000	MIO Pin 37 Control
MIO_PIN_38	0XF8000798	32	RW	0x000000	MIO Pin 38 Control
MIO_PIN_39	0XF800079C	32	RW	0x000000	MIO Pin 39 Control
MIO_PIN_48	0XF80007C0	32	RW	0x000000	MIO Pin 48 Control
MIO_PIN_49	0XF80007C4	32	RW	0x000000	MIO Pin 49 Control
MIO_PIN_52	0XF80007D0	32	RW	0x000000	MIO Pin 52 Control
MIO_PIN_53	0XF80007D4	32	RW	0x000000	MIO Pin 53 Control
SLCR_LOCK	0XF8000004	32	WO	0x000000	SLCR Write Protection Lock

ps7_mio_init_data_3_0

SLCR SETTINGS

Register ( slcr )SLCR_UNLOCK

Register Name

Address

Width

Type

Reset Value

Description

Register Name	Address	Width	Type	Reset Value	Description
SLCR_UNLOCK	0XF8000008	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
UNLOCK_KEY	15:0	ffff	df0d	df0d	Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero.
SLCR_UNLOCK@0XF8000008	31:0	ffff		df0d	SLCR Write Protection Unlock

OCM REMAPPING

MIO PROGRAMMING

Register ( slcr )MIO_PIN_00

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_00	0XF8000700	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Tri-state enable, active high. 0: disable 1: enable
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select, Output
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: reserved
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0, Output 10: NAND Flash Chip Select, Output 11: SDIO 0 Power Control, Output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 0 (bank 0), Input/Output others: reserved
Speed	8:8	100	0	0	Select IO Buffer Edge Rate, applicable when IO_Type is LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge
IO_Type	11:9	e00	3	600	Select the IO Buffer Type. 000: Reserved 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL
PULLUP	12:12	1000	1	1000	Enables Pullup on IO Buffer pin 0: disable 1: enable
DisableRcvr	13:13	2000	0	0	Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable
MIO_PIN_00@0XF8000700	31:0	3fff		1600	MIO Pin 0 Control

Register ( slcr )MIO_PIN_01

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_01	0XF8000704	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	1	2	Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select, Output
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: reserved
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25, Output 10: SRAM/NOR Chip Select 1, Output 11: SDIO 1 Power Control, Output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 1 (bank 0), Input/Output others: reserved
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULLUP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_01@0XF8000704	31:0	3fff		1602	MIO Pin 1 Control

Register ( slcr )MIO_PIN_02

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_02	0XF8000708	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	1	2	Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0, Input/Output
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8, Output
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn, Output 11: SDIO 0 Power Control, Output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 2 (bank 0), Input/Output others: reserved
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	0	0	Operates the same as MIO_PIN_00[PULLUP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_02@0XF8000708	31:0	3fff		602	MIO Pin 2 Control

Register ( slcr )MIO_PIN_03

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_03	0XF800070C	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	1	2	Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1, Input/Output
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9, Output
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0, Input/Output 10: NAND WE_B, Output 11: SDIO 1 Card Power, Output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 3 (bank 0), Input/Output others: reserved
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	0	0	Operates the same as MIO_PIN_00[PULLUP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_03@0XF800070C	31:0	3fff		602	MIO Pin 3 Control

Register ( slcr )MIO_PIN_04

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_04	0XF8000710	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	1	2	Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2, Input/Output
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10, Output
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1, Input/Output 10: NAND Flash IO Bit 2, Input/Output 11: SDIO 0 Power Control, Output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 4 (bank 0), Input/Output others: reserved
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	0	0	Operates the same as MIO_PIN_00[PULLUP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_04@0XF8000710	31:0	3fff		602	MIO Pin 4 Control

Register ( slcr )MIO_PIN_05

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_05	0XF8000714	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	1	2	Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3, Input/Output
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11, Output
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2, Input/Output 10: NAND Flash IO Bit 0, Input/Output 11: SDIO 1 Power Control, Output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 5 (bank 0), Input/Output others: reserved
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	0	0	Operates the same as MIO_PIN_00[PULLUP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_05@0XF8000714	31:0	3fff		602	MIO Pin 5 Control

Register ( slcr )MIO_PIN_06

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_06	0XF8000718	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	1	2	Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock, Output
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12, Output
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3, Input/Output 10: NAND Flash IO Bit 1, Input/Output 11: SDIO 0 Power Control, Output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 6 (bank 0), Input/Output others: reserved
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	0	0	Operates the same as MIO_PIN_00[PULLUP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_06@0XF8000718	31:0	3fff		602	MIO Pin 6 Control

Register ( slcr )MIO_PIN_07

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_07	0XF800071C	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: reserved
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13, Output
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B, Output 10: NAND Flash CLE_B, Output 11: SDIO 1 Power Control, Output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 7 (bank 0), Output-only others: reserved
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	0	0	Operates the same as MIO_PIN_00[PULLUP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_07@0XF800071C	31:0	3fff		600	MIO Pin 7 Control

Register ( slcr )MIO_PIN_08

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_08	0XF8000720	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Clock, Output
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14, Output
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash RD_B, Output 11: SDIO 0 Power Control, Output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 8 (bank 0), Output-only 001: CAN 1 Tx, Output 010: SRAM/NOR BLS_B, Output 011 to 110: reserved 111: UART 1 TxD, Output
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	0	0	Operates the same as MIO_PIN_00[PULLUP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_08@0XF8000720	31:0	3fff		600	MIO Pin 8 Control

Register ( slcr )MIO_PIN_09

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_09	0XF8000724	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock, Output
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15, Output
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6, Input/Output 10: NAND Flash IO Bit 4, Input/Output 11: SDIO 1 Power Control, Output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 9 (bank 0), Input/Output 001: CAN 1 Rx, Input 010 to 110: reserved 111: UART 1 RxD, Input
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULLUP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_09@0XF8000724	31:0	3fff		1600	MIO Pin 9 Control

Register ( slcr )MIO_PIN_10

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_10	0XF8000728	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0, Input/Output
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7, Input/Output 10: NAND Flash IO Bit 5, Input/Output 11: SDIO 0 Power Control, Output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 10 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULLUP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_10@0XF8000728	31:0	3fff		1600	MIO Pin 10 Control

Register ( slcr )MIO_PIN_11

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_11	0XF800072C	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1, Input/Output
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4, Input/Output 10: NAND Flash IO Bit 6, Input/Output 11: SDIO 1 Power Control, Output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 11 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULLUP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_11@0XF800072C	31:0	3fff		1600	MIO Pin 11 Control

Register ( slcr )MIO_PIN_12

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_12	0XF8000730	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2, Input/Output
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock, Output
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait, Input 10: NAND Flash IO Bit 7, Input/Output 11: SDIO 0 Power Control, Output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 12 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULLUP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_12@0XF8000730	31:0	3fff		1600	MIO Pin 12 Control

Register ( slcr )MIO_PIN_13

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_13	0XF8000734	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3, Input/Output
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5, Input/Output 10: NAND Flash IO Bit 3, Input/Output 11: SDIO 1 Power Control, Output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 13 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULLUP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_13@0XF8000734	31:0	3fff		1600	MIO Pin 13 Control

Register ( slcr )MIO_PIN_14

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_14	0XF8000738	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1= Not Used
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy, Input 11: SDIO 0 Power Control, Output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 14 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 slave select 1, Output 110: reserved 111: UART 0 RxD, Input
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULLUP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_14@0XF8000738	31:0	3fff		1600	MIO Pin 14 Control

Register ( slcr )MIO_PIN_15

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_15	0XF800073C	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1= Not Used
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0, Output 10: reserved 11: SDIO 1 Power Control, Output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 15 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULLUP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_15@0XF800073C	31:0	3fff		1600	MIO Pin 15 Control

Register ( slcr )MIO_PIN_28

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_28	0XF8000770	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock, Output
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4, Input/Output
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13, Output 10: reserved 11: SDIO 0 Power Control, Output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 28 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULLUP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_28@0XF8000770	31:0	3fff		1600	MIO Pin 28 Control

Register ( slcr )MIO_PIN_29

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_29	0XF8000774	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0, Output
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction, Input
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14, Output 10: reserved 11: SDIO 1 Power Control, Output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 29 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULLUP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_29@0XF8000774	31:0	3fff		1600	MIO Pin 29 Control

Register ( slcr )MIO_PIN_30

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_30	0XF8000778	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1, Output
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop, Output
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15, Output 10: reserved 11: SDIO 0 Power Control, Output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 30 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULLUP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_30@0XF8000778	31:0	3fff		1600	MIO Pin 30 Control

Register ( slcr )MIO_PIN_31

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_31	0XF800077C	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2, Output
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next, Input
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16, Output 10: reserved 11: SDIO 1 Power Control, Output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 31 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULLUP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_31@0XF800077C	31:0	3fff		1600	MIO Pin 31 Control

Register ( slcr )MIO_PIN_32

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_32	0XF8000780	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3, Output
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0, Input/Output
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17, Output 10: reserved 11: SDIO 0 Power Control, Output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 32 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULLUP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_32@0XF8000780	31:0	3fff		1600	MIO Pin 32 Control

Register ( slcr )MIO_PIN_33

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_33	0XF8000784	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control, Output
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1, Input/Output
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18, Output 10: reserved 11: SDIO 1 Power Control, Output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 33 (Bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULLUP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_33@0XF8000784	31:0	3fff		1600	MIO Pin 33 Control

Register ( slcr )MIO_PIN_34

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_34	0XF8000788	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock, Input
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2, Input/Output
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19, Output 10: reserved 11: SDIO 0 Power Control, Output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 34 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 110: reserved 111: UART 0 RxD, Input
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULLUP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_34@0XF8000788	31:0	3fff		1600	MIO Pin 34 Control

Register ( slcr )MIO_PIN_35

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_35	0XF800078C	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0, Input
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3, Input/Output
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20, Output 10: reserved 11: SDIO 1 Power Control, Output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 35 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULLUP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_35@0XF800078C	31:0	3fff		1600	MIO Pin 35 Control

Register ( slcr )MIO_PIN_36

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_36	0XF8000790	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock, Input/Output
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21, Output 10: reserved 11: SDIO 0 Power Control, Output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 36 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Clock, Input/Output 110: reserved 111: UART 1 TxD, Output
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULLUP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_36@0XF8000790	31:0	3fff		1600	MIO Pin 36 Control

Register ( slcr )MIO_PIN_37

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_37	0XF8000794	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 2, Input
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5, Input/Output
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22, Output 10: reserved 11: SDIO 1 Power Control, Output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 37 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULLUP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_37@0XF8000794	31:0	3fff		1600	MIO Pin 37 Control

Register ( slcr )MIO_PIN_38

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_38	0XF8000798	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3, Input
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6, Input/Output
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23, Output 10: reserved 11: SDIO 0 Power Control, Output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 38 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULLUP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_38@0XF8000798	31:0	3fff		1600	MIO Pin 38 Control

Register ( slcr )MIO_PIN_39

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_39	0XF800079C	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control, Input
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7, Input/Output
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24, Output 10: reserved 11: SDIO 1 Power Control, Output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 39 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULLUP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_39@0XF800079C	31:0	3fff		1600	MIO Pin 39 Control

Register ( slcr )MIO_PIN_48

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_48	0XF80007C0	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: reserved
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock, Input/Output
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 48 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULLUP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_48@0XF80007C0	31:0	3fff		1600	MIO Pin 48 Control

Register ( slcr )MIO_PIN_49

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_49	0XF80007C4	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: reserved
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5, Input/Output
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 49 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULLUP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_49@0XF80007C4	31:0	3fff		1600	MIO Pin 49 Control

Register ( slcr )MIO_PIN_52

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_52	0XF80007D0	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: reserved
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: reserved
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 52 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: SWDT Clock, Input 100: MDIO 0 Clock, Output 101: MDIO 1 Clock, Output 110: reserved 111: UART 1 TxD, Output
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULLUP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_52@0XF80007D0	31:0	3fff		1600	MIO Pin 52 Control

Register ( slcr )MIO_PIN_53

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_53	0XF80007D4	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: reserved
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: reserved
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 53 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: SWDT Reset, Output 100: MDIO 0 Data, Input/Output 101: MDIO 1 Data, Input/Output 110: reserved 111: UART 1 RxD, Input
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULLUP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_53@0XF80007D4	31:0	3fff		1600	MIO Pin 53 Control

LOCK IT BACK

Register ( slcr )SLCR_LOCK

Register Name	Address	Width	Type	Reset Value	Description
SLCR_LOCK	0XF8000004	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
LOCK_KEY	15:0	ffff	767b	767b	Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero.
SLCR_LOCK@0XF8000004	31:0	ffff		767b	SLCR Write Protection Lock

ps7_peripherals_init_data_3_0

Register Name	Address	Width	Type	Reset Value	Description
SLCR_UNLOCK	0XF8000008	32	WO	0x000000	SLCR Write Protection Unlock
SLCR_LOCK	0XF8000004	32	WO	0x000000	SLCR Write Protection Lock
Baud_rate_divider_reg0	0XE0000034	32	RW	0x000000	Baud Rate Divider Register
Baud_rate_gen_reg0	0XE0000018	32	RW	0x000000	Baud Rate Generator Register.
Control_reg0	0XE0000000	32	RW	0x000000	UART Control Register
mode_reg0	0XE0000004	32	RW	0x000000	UART Mode Register
Config_reg	0XE000D000	32	RW	0x000000	SPI configuration register
CTRL	0XF8007000	32	RW	0x000000	Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.

ps7_peripherals_init_data_3_0

SLCR SETTINGS

Register ( slcr )SLCR_UNLOCK

Register Name

Address

Width

Type

Reset Value

Description

Register Name	Address	Width	Type	Reset Value	Description
SLCR_UNLOCK	0XF8000008	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
UNLOCK_KEY	15:0	ffff	df0d	df0d	Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero.
SLCR_UNLOCK@0XF8000008	31:0	ffff		df0d	SLCR Write Protection Unlock

LOCK IT BACK

Register ( slcr )SLCR_LOCK

Register Name	Address	Width	Type	Reset Value	Description
SLCR_LOCK	0XF8000004	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
LOCK_KEY	15:0	ffff	767b	767b	Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero.
SLCR_LOCK@0XF8000004	31:0	ffff		767b	SLCR Write Protection Lock

SRAM/NOR SET OPMODE

UART REGISTERS

Register ( slcr )Baud_rate_divider_reg0

Register Name	Address	Width	Type	Reset Value	Description
Baud_rate_divider_reg0	0XE0000034	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
BDIV	7:0	ff	6	6	Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
Baud_rate_divider_reg0@0XE0000034	31:0	ff		6	Baud Rate Divider Register

Register ( slcr )Baud_rate_gen_reg0

Register Name	Address	Width	Type	Reset Value	Description
Baud_rate_gen_reg0	0XE0000018	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
CD	15:0	ffff	7c	7c	Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample
Baud_rate_gen_reg0@0XE0000018	31:0	ffff		7c	Baud Rate Generator Register.

Register ( slcr )Control_reg0

Register Name	Address	Width	Type	Reset Value	Description
Control_reg0	0XE0000000	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
STPBRK	8:8	100	0	0	Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. It can be set regardless of the value of STTBRK.
STTBRK	7:7	80	0	0	Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.
RSTTO	6:6	40	0	0	Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has completed.
TXDIS	5:5	20	0	0	Transmit disable: 0: enable transmitter 1: disable transmitter
TXEN	4:4	10	1	10	Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.
RXDIS	3:3	8	0	0	Receive disable: 0: enable 1: disable, regardless of the value of RXEN
RXEN	2:2	4	1	4	Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.
TXRES	1:1	2	1	2	Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded This bit is self clearing once the reset has completed.
RXRES	0:0	1	1	1	Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit is self clearing once the reset has completed.
Control_reg0@0XE0000000	31:0	1ff		17	UART Control Register

Register ( slcr )mode_reg0

Register Name	Address	Width	Type	Reset Value	Description
mode_reg0	0XE0000004	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
CHMODE	9:8	300	0	0	Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback
NBSTOP	7:6	c0	0	0	Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved
PAR	5:3	38	4	20	Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity
CHRL	2:1	6	0	0	Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits
CLKS	0:0	1	0	0	Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock source is uart_ref_clk 1: clock source is uart_ref_clk/8
mode_reg0@0XE0000004	31:0	3ff		20	UART Mode Register

QSPI REGISTERS

Register ( slcr )Config_reg

Register Name	Address	Width	Type	Reset Value	Description
Config_reg	0XE000D000	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
Holdb_dr	19:19	80000	1	80000	If set, Holdb and WPn pins are actively driven by the qspi controller in 1-bit and 2-bit modes . If not set, then external pull up is required on HOLDb and WPn pins . Note that this bit doesn't affect the quad(4-bit) mode as Controller always drives these pins in quad mode. It is highly recommended to set this bit always(irrespective of mode of operation) while using QSPI
Config_reg@0XE000D000	31:0	80000		80000	SPI configuration register

PL POWER ON RESET REGISTERS

Register ( slcr )CTRL

Register Name	Address	Width	Type	Reset Value	Description
CTRL	0XF8007000	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PCFG_POR_CNT_4K	29:29	20000000	0	0	This register controls which POR timer the PL will use for power-up. 0 - Use 64k timer 1 - Use 4k timer
CTRL@0XF8007000	31:0	20000000		0	Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.

SMC TIMING CALCULATION REGISTER UPDATE

NAND SET CYCLE

OPMODE

DIRECT COMMAND

SRAM/NOR CS0 SET CYCLE

DIRECT COMMAND

NOR CS0 BASE ADDRESS

SRAM/NOR CS1 SET CYCLE

DIRECT COMMAND

NOR CS1 BASE ADDRESS

USB RESET

ENET RESET

I2C RESET

NOR CHIP SELECT

DIR MODE BANK 0

MASK_DATA_0_LSW HIGH BANK [15:0]

OUTPUT ENABLE BANK 0

ps7_post_config_3_0

Register Name	Address	Width	Type	Reset Value	Description
SLCR_UNLOCK	0XF8000008	32	WO	0x000000	SLCR Write Protection Unlock
LVL_SHFTR_EN	0XF8000900	32	RW	0x000000	Level Shifters Enable
FPGA_RST_CTRL	0XF8000240	32	RW	0x000000	FPGA Software Reset Control
SLCR_LOCK	0XF8000004	32	WO	0x000000	SLCR Write Protection Lock

ps7_post_config_3_0

SLCR SETTINGS

Register ( slcr )SLCR_UNLOCK

Register Name

Address

Width

Type

Reset Value

Description

Register Name	Address	Width	Type	Reset Value	Description
SLCR_UNLOCK	0XF8000008	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
UNLOCK_KEY	15:0	ffff	df0d	df0d	Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero.
SLCR_UNLOCK@0XF8000008	31:0	ffff		df0d	SLCR Write Protection Unlock

ENABLING LEVEL SHIFTER

Register ( slcr )LVL_SHFTR_EN

Register Name	Address	Width	Type	Reset Value	Description
LVL_SHFTR_EN	0XF8000900	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
USER_LVL_INP_EN_0	3:3	8	1	8	Level shifter enable to drive signals from PL to PS
USER_LVL_OUT_EN_0	2:2	4	1	4	Level shifter enable to drive signals from PS to PL
USER_LVL_INP_EN_1	1:1	2	1	2	Level shifter enable to drive signals from PL to PS
USER_LVL_OUT_EN_1	0:0	1	1	1	Level shifter enable to drive signals from PS to PL
LVL_SHFTR_EN@0XF8000900	31:0	f		f	Level Shifters Enable

FPGA RESETS TO 0

Register ( slcr )FPGA_RST_CTRL

Register Name	Address	Width	Type	Reset Value	Description
FPGA_RST_CTRL	0XF8000240	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
reserved_3	31:25	fe000000	0	0	Reserved. Writes are ignored, read data is zero.
reserved_FPGA_ACP_RST	24:24	1000000	0	0	Reserved. Do not modify.
reserved_FPGA_AXDS3_RST	23:23	800000	0	0	Reserved. Do not modify.
reserved_FPGA_AXDS2_RST	22:22	400000	0	0	Reserved. Do not modify.
reserved_FPGA_AXDS1_RST	21:21	200000	0	0	Reserved. Do not modify.
reserved_FPGA_AXDS0_RST	20:20	100000	0	0	Reserved. Do not modify.
reserved_2	19:18	c0000	0	0	Reserved. Writes are ignored, read data is zero.
reserved_FSSW1_FPGA_RST	17:17	20000	0	0	Reserved. Do not modify.
reserved_FSSW0_FPGA_RST	16:16	10000	0	0	Reserved. Do not modify.
reserved_1	15:14	c000	0	0	Reserved. Writes are ignored, read data is zero.
reserved_FPGA_FMSW1_RST	13:13	2000	0	0	Reserved. Do not modify.
reserved_FPGA_FMSW0_RST	12:12	1000	0	0	Reserved. Do not modify.
reserved_FPGA_DMA3_RST	11:11	800	0	0	Reserved. Do not modify.
reserved_FPGA_DMA2_RST	10:10	400	0	0	Reserved. Do not modify.
reserved_FPGA_DMA1_RST	9:9	200	0	0	Reserved. Do not modify.
reserved_FPGA_DMA0_RST	8:8	100	0	0	Reserved. Do not modify.
reserved	7:4	f0	0	0	Reserved. Writes are ignored, read data is zero.
FPGA3_OUT_RST	3:3	8	0	0	PL Reset 3 (FCLKRESETN3 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN3 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state)
FPGA2_OUT_RST	2:2	4	0	0	PL Reset 2 (FCLKRESETN2 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN2 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state)
FPGA1_OUT_RST	1:1	2	0	0	PL Reset 1 (FCLKRESETN1 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN1 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state)
FPGA0_OUT_RST	0:0	1	0	0	PL Reset 0 (FCLKRESETN0 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN0 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state)
FPGA_RST_CTRL@0XF8000240	31:0	ffffffff		0	FPGA Software Reset Control

AFI REGISTERS

AFI0 REGISTERS

AFI1 REGISTERS

AFI2 REGISTERS

AFI3 REGISTERS

AFI2 SECURE REGISTER

LOCK IT BACK

Register ( slcr )SLCR_LOCK

Register Name	Address	Width	Type	Reset Value	Description
SLCR_LOCK	0XF8000004	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
LOCK_KEY	15:0	ffff	767b	767b	Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero.
SLCR_LOCK@0XF8000004	31:0	ffff		767b	SLCR Write Protection Lock

ps7_debug_3_0

Register Name	Address	Width	Type	Reset Value	Description
LAR	0XF8898FB0	32	WO	0x000000	Lock Access Register
LAR	0XF8899FB0	32	WO	0x000000	Lock Access Register
LAR	0XF8809FB0	32	WO	0x000000	Lock Access Register

ps7_debug_3_0

CROSS TRIGGER CONFIGURATIONS

UNLOCKING CTI REGISTERS

Register ( slcr )LAR

Register Name

Address

Width

Type

Reset Value

Description

Register Name	Address	Width	Type	Reset Value	Description
LAR	0XF8898FB0	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
KEY	31:0	ffffffff	c5acce55	c5acce55	Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.
LAR@0XF8898FB0	31:0	ffffffff		c5acce55	Lock Access Register

Register ( slcr )LAR

Register Name	Address	Width	Type	Reset Value	Description
LAR	0XF8899FB0	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
KEY	31:0	ffffffff	c5acce55	c5acce55	Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.
LAR@0XF8899FB0	31:0	ffffffff		c5acce55	Lock Access Register

Register ( slcr )LAR

Register Name	Address	Width	Type	Reset Value	Description
LAR	0XF8809FB0	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
KEY	31:0	ffffffff	c5acce55	c5acce55	Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.
LAR@0XF8809FB0	31:0	ffffffff		c5acce55	Lock Access Register

ENABLING CTI MODULES AND CHANNELS

MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

ps7_pll_init_data_2_0

Register Name	Address	Width	Type	Reset Value	Description
SLCR_UNLOCK	0XF8000008	32	WO	0x000000	SLCR Write Protection Unlock
ARM_PLL_CFG	0XF8000110	32	RW	0x000000	ARM PLL Configuration
ARM_PLL_CTRL	0XF8000100	32	RW	0x000000	ARM PLL Control
ARM_PLL_CTRL	0XF8000100	32	RW	0x000000	ARM PLL Control
ARM_PLL_CTRL	0XF8000100	32	RW	0x000000	ARM PLL Control
ARM_PLL_CTRL	0XF8000100	32	RW	0x000000	ARM PLL Control
ARM_PLL_CTRL	0XF8000100	32	RW	0x000000	ARM PLL Control
ARM_CLK_CTRL	0XF8000120	32	RW	0x000000	CPU Clock Control
DDR_PLL_CFG	0XF8000114	32	RW	0x000000	DDR PLL Configuration
DDR_PLL_CTRL	0XF8000104	32	RW	0x000000	DDR PLL Control
DDR_PLL_CTRL	0XF8000104	32	RW	0x000000	DDR PLL Control
DDR_PLL_CTRL	0XF8000104	32	RW	0x000000	DDR PLL Control
DDR_PLL_CTRL	0XF8000104	32	RW	0x000000	DDR PLL Control
DDR_PLL_CTRL	0XF8000104	32	RW	0x000000	DDR PLL Control
DDR_CLK_CTRL	0XF8000124	32	RW	0x000000	DDR Clock Control
IO_PLL_CFG	0XF8000118	32	RW	0x000000	IO PLL Configuration
IO_PLL_CTRL	0XF8000108	32	RW	0x000000	IO PLL Control
IO_PLL_CTRL	0XF8000108	32	RW	0x000000	IO PLL Control
IO_PLL_CTRL	0XF8000108	32	RW	0x000000	IO PLL Control
IO_PLL_CTRL	0XF8000108	32	RW	0x000000	IO PLL Control
IO_PLL_CTRL	0XF8000108	32	RW	0x000000	IO PLL Control
SLCR_LOCK	0XF8000004	32	WO	0x000000	SLCR Write Protection Lock

ps7_pll_init_data_2_0

SLCR SETTINGS

Register ( slcr )SLCR_UNLOCK

Register Name

Address

Width

Type

Reset Value

Description

Register Name	Address	Width	Type	Reset Value	Description
SLCR_UNLOCK	0XF8000008	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
UNLOCK_KEY	15:0	ffff	df0d	df0d	When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero.
SLCR_UNLOCK@0XF8000008	31:0	ffff		df0d	SLCR Write Protection Unlock

PLL SLCR REGISTERS

ARM PLL INIT

Register ( slcr )ARM_PLL_CFG

Register Name	Address	Width	Type	Reset Value	Description
ARM_PLL_CFG	0XF8000110	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_RES	7:4	f0	2	20	Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control
PLL_CP	11:8	f00	2	200	Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control
LOCK_CNT	21:12	3ff000	fa	fa000	Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked.
ARM_PLL_CFG@0XF8000110	31:0	3ffff0		fa220	ARM PLL Configuration

UPDATE FB_DIV

Register ( slcr )ARM_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
ARM_PLL_CTRL	0XF8000100	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_FDIV	18:12	7f000	28	28000	Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state.
ARM_PLL_CTRL@0XF8000100	31:0	7f000		28000	ARM PLL Control

BY PASS PLL

Register ( slcr )ARM_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
ARM_PLL_CTRL	0XF8000100	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_BYPASS_FORCE	4:4	10	1	10	ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping.
ARM_PLL_CTRL@0XF8000100	31:0	10		10	ARM PLL Control

ASSERT RESET

Register ( slcr )ARM_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
ARM_PLL_CTRL	0XF8000100	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_RESET	0:0	1	1	1	Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using.
ARM_PLL_CTRL@0XF8000100	31:0	1		1	ARM PLL Control

DEASSERT RESET

Register ( slcr )ARM_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
ARM_PLL_CTRL	0XF8000100	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_RESET	0:0	1	0	0	Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using.
ARM_PLL_CTRL@0XF8000100	31:0	1		0	ARM PLL Control

CHECK PLL STATUS

Register ( slcr )PLL_STATUS

Register Name	Address	Width	Type	Reset Value	Description
PLL_STATUS	0XF800010C	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
ARM_PLL_LOCK	0:0	1	1	1	ARM PLL lock status: 0: not locked, 1: locked
PLL_STATUS@0XF800010C	31:0	1		1	tobe

REMOVE PLL BY PASS

Register ( slcr )ARM_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
ARM_PLL_CTRL	0XF8000100	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_BYPASS_FORCE	4:4	10	0	0	ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping.
ARM_PLL_CTRL@0XF8000100	31:0	10		0	ARM PLL Control

Register ( slcr )ARM_CLK_CTRL

Register Name	Address	Width	Type	Reset Value	Description
ARM_CLK_CTRL	0XF8000120	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
SRCSEL	5:4	30	0	0	Select the source used to generate the CPU clock: 0x: CPU PLL 10: divided DDR PLL 11: IO PLL
DIVISOR	13:8	3f00	2	200	Frequency divisor for the CPU clock source.
CPU_6OR4XCLKACT	24:24	1000000	1	1000000	CPU_6x4x Clock control: 0: disable, 1: enable
CPU_3OR2XCLKACT	25:25	2000000	1	2000000	CPU_3x2x Clock control: 0: disable, 1: enable
CPU_2XCLKACT	26:26	4000000	1	4000000	CPU_2x Clock control: 0: disable, 1: enable
CPU_1XCLKACT	27:27	8000000	1	8000000	CPU_1x Clock control: 0: disable, 1: enable
CPU_PERI_CLKACT	28:28	10000000	1	10000000	Clock active: 0: Clock is disabled 1: Clock is enabled
ARM_CLK_CTRL@0XF8000120	31:0	1f003f30		1f000200	CPU Clock Control

DDR PLL INIT

Register ( slcr )DDR_PLL_CFG

Register Name	Address	Width	Type	Reset Value	Description
DDR_PLL_CFG	0XF8000114	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_RES	7:4	f0	2	20	Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control.
PLL_CP	11:8	f00	2	200	Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control.
LOCK_CNT	21:12	3ff000	12c	12c000	Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked.
DDR_PLL_CFG@0XF8000114	31:0	3ffff0		12c220	DDR PLL Configuration

UPDATE FB_DIV

Register ( slcr )DDR_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
DDR_PLL_CTRL	0XF8000104	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_FDIV	18:12	7f000	20	20000	Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state.
DDR_PLL_CTRL@0XF8000104	31:0	7f000		20000	DDR PLL Control

BY PASS PLL

Register ( slcr )DDR_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
DDR_PLL_CTRL	0XF8000104	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_BYPASS_FORCE	4:4	10	1	10	Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed
DDR_PLL_CTRL@0XF8000104	31:0	10		10	DDR PLL Control

ASSERT RESET

Register ( slcr )DDR_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
DDR_PLL_CTRL	0XF8000104	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_RESET	0:0	1	1	1	Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using.
DDR_PLL_CTRL@0XF8000104	31:0	1		1	DDR PLL Control

DEASSERT RESET

Register ( slcr )DDR_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
DDR_PLL_CTRL	0XF8000104	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_RESET	0:0	1	0	0	Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using.
DDR_PLL_CTRL@0XF8000104	31:0	1		0	DDR PLL Control

CHECK PLL STATUS

Register ( slcr )PLL_STATUS

Register Name	Address	Width	Type	Reset Value	Description
PLL_STATUS	0XF800010C	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
DDR_PLL_LOCK	1:1	2	1	2	DDR PLL lock status: 0: not locked, 1: locked
PLL_STATUS@0XF800010C	31:0	2		2	tobe

REMOVE PLL BY PASS

Register ( slcr )DDR_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
DDR_PLL_CTRL	0XF8000104	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_BYPASS_FORCE	4:4	10	0	0	Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed
DDR_PLL_CTRL@0XF8000104	31:0	10		0	DDR PLL Control

Register ( slcr )DDR_CLK_CTRL

Register Name	Address	Width	Type	Reset Value	Description
DDR_CLK_CTRL	0XF8000124	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
DDR_3XCLKACT	0:0	1	1	1	DDR_3x Clock control: 0: disable, 1: enable
DDR_2XCLKACT	1:1	2	1	2	DDR_2x Clock control: 0: disable, 1: enable
DDR_3XCLK_DIVISOR	25:20	3f00000	2	200000	Frequency divisor for the ddr_3x clock
DDR_2XCLK_DIVISOR	31:26	fc000000	3	c000000	Frequency divisor for the ddr_2x clock
DDR_CLK_CTRL@0XF8000124	31:0	fff00003		c200003	DDR Clock Control

IO PLL INIT

Register ( slcr )IO_PLL_CFG

Register Name	Address	Width	Type	Reset Value	Description
IO_PLL_CFG	0XF8000118	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_RES	7:4	f0	4	40	Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control.
PLL_CP	11:8	f00	2	200	Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control.
LOCK_CNT	21:12	3ff000	fa	fa000	Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked.
IO_PLL_CFG@0XF8000118	31:0	3ffff0		fa240	IO PLL Configuration

UPDATE FB_DIV

Register ( slcr )IO_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
IO_PLL_CTRL	0XF8000108	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_FDIV	18:12	7f000	30	30000	Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state.
IO_PLL_CTRL@0XF8000108	31:0	7f000		30000	IO PLL Control

BY PASS PLL

Register ( slcr )IO_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
IO_PLL_CTRL	0XF8000108	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_BYPASS_FORCE	4:4	10	1	10	Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed
IO_PLL_CTRL@0XF8000108	31:0	10		10	IO PLL Control

ASSERT RESET

Register ( slcr )IO_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
IO_PLL_CTRL	0XF8000108	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_RESET	0:0	1	1	1	Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using.
IO_PLL_CTRL@0XF8000108	31:0	1		1	IO PLL Control

DEASSERT RESET

Register ( slcr )IO_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
IO_PLL_CTRL	0XF8000108	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_RESET	0:0	1	0	0	Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using.
IO_PLL_CTRL@0XF8000108	31:0	1		0	IO PLL Control

CHECK PLL STATUS

Register ( slcr )PLL_STATUS

Register Name	Address	Width	Type	Reset Value	Description
PLL_STATUS	0XF800010C	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
IO_PLL_LOCK	2:2	4	1	4	IO PLL lock status: 0: not locked, 1: locked
PLL_STATUS@0XF800010C	31:0	4		4	tobe

REMOVE PLL BY PASS

Register ( slcr )IO_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
IO_PLL_CTRL	0XF8000108	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_BYPASS_FORCE	4:4	10	0	0	Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed
IO_PLL_CTRL@0XF8000108	31:0	10		0	IO PLL Control

LOCK IT BACK

Register ( slcr )SLCR_LOCK

Register Name	Address	Width	Type	Reset Value	Description
SLCR_LOCK	0XF8000004	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
LOCK_KEY	15:0	ffff	767b	767b	When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero.
SLCR_LOCK@0XF8000004	31:0	ffff		767b	SLCR Write Protection Lock

ps7_clock_init_data_2_0

Register Name	Address	Width	Type	Reset Value	Description
SLCR_UNLOCK	0XF8000008	32	WO	0x000000	SLCR Write Protection Unlock
DCI_CLK_CTRL	0XF8000128	32	RW	0x000000	DCI clock control
LQSPI_CLK_CTRL	0XF800014C	32	RW	0x000000	Quad SPI Ref Clock Control
UART_CLK_CTRL	0XF8000154	32	RW	0x000000	UART Ref Clock Control
PCAP_CLK_CTRL	0XF8000168	32	RW	0x000000	PCAP Clock Control
FPGA0_CLK_CTRL	0XF8000170	32	RW	0x000000	PL Clock 0 Output control
CLK_621_TRUE	0XF80001C4	32	RW	0x000000	CPU Clock Ratio Mode select
APER_CLK_CTRL	0XF800012C	32	RW	0x000000	AMBA Peripheral Clock Control
SLCR_LOCK	0XF8000004	32	WO	0x000000	SLCR Write Protection Lock

ps7_clock_init_data_2_0

SLCR SETTINGS

Register ( slcr )SLCR_UNLOCK

Register Name

Address

Width

Type

Reset Value

Description

Register Name	Address	Width	Type	Reset Value	Description
SLCR_UNLOCK	0XF8000008	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
UNLOCK_KEY	15:0	ffff	df0d	df0d	When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero.
SLCR_UNLOCK@0XF8000008	31:0	ffff		df0d	SLCR Write Protection Unlock

CLOCK CONTROL SLCR REGISTERS

Register ( slcr )DCI_CLK_CTRL

Register Name	Address	Width	Type	Reset Value	Description
DCI_CLK_CTRL	0XF8000128	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
CLKACT	0:0	1	1	1	DCI clock control - 0: disable, 1: enable
DIVISOR0	13:8	3f00	f	f00	Provides the divisor used to divide the source clock to generate the required generated clock frequency.
DIVISOR1	25:20	3f00000	7	700000	Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider
DCI_CLK_CTRL@0XF8000128	31:0	3f03f01		700f01	DCI clock control

Register ( slcr )LQSPI_CLK_CTRL

Register Name	Address	Width	Type	Reset Value	Description
LQSPI_CLK_CTRL	0XF800014C	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
CLKACT	0:0	1	1	1	Quad SPI Controller Reference Clock control 0: disable, 1: enable
SRCSEL	5:4	30	0	0	Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL
DIVISOR	13:8	3f00	8	800	Divisor for Quad SPI Controller source clock.
LQSPI_CLK_CTRL@0XF800014C	31:0	3f31		801	Quad SPI Ref Clock Control

Register ( slcr )UART_CLK_CTRL

Register Name	Address	Width	Type	Reset Value	Description
UART_CLK_CTRL	0XF8000154	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
CLKACT0	0:0	1	1	1	UART 0 Reference clock control. 0: disable, 1: enable
CLKACT1	1:1	2	0	0	UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled
SRCSEL	5:4	30	0	0	Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL
DIVISOR	13:8	3f00	10	1000	Divisor for UART Controller source clock.
UART_CLK_CTRL@0XF8000154	31:0	3f33		1001	UART Ref Clock Control

TRACE CLOCK

Register ( slcr )PCAP_CLK_CTRL

Register Name	Address	Width	Type	Reset Value	Description
PCAP_CLK_CTRL	0XF8000168	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
CLKACT	0:0	1	1	1	Clock active: 0: Clock is disabled 1: Clock is enabled
SRCSEL	5:4	30	0	0	Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.
DIVISOR	13:8	3f00	8	800	Provides the divisor used to divide the source clock to generate the required generated clock frequency.
PCAP_CLK_CTRL@0XF8000168	31:0	3f31		801	PCAP Clock Control

Register ( slcr )FPGA0_CLK_CTRL

Register Name	Address	Width	Type	Reset Value	Description
FPGA0_CLK_CTRL	0XF8000170	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
SRCSEL	5:4	30	0	0	Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.
DIVISOR0	13:8	3f00	8	800	Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider.
DIVISOR1	25:20	3f00000	4	400000	Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide
FPGA0_CLK_CTRL@0XF8000170	31:0	3f03f30		400800	PL Clock 0 Output control

Register ( slcr )CLK_621_TRUE

Register Name	Address	Width	Type	Reset Value	Description
CLK_621_TRUE	0XF80001C4	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
CLK_621_TRUE	0:0	1	1	1	Select the CPU clock ration: 0: 4:2:1 1: 6:2:1
CLK_621_TRUE@0XF80001C4	31:0	1		1	CPU Clock Ratio Mode select

Register ( slcr )APER_CLK_CTRL

Register Name	Address	Width	Type	Reset Value	Description
APER_CLK_CTRL	0XF800012C	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
DMA_CPU_2XCLKACT	0:0	1	1	1	DMA controller AMBA Clock control 0: disable, 1: enable
USB0_CPU_1XCLKACT	2:2	4	1	4	USB controller 0 AMBA Clock control 0: disable, 1: enable
USB1_CPU_1XCLKACT	3:3	8	1	8	USB controller 1 AMBA Clock control 0: disable, 1: enable
GEM0_CPU_1XCLKACT	6:6	40	0	0	Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable
GEM1_CPU_1XCLKACT	7:7	80	0	0	Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable
SDI0_CPU_1XCLKACT	10:10	400	0	0	SDIO controller 0 AMBA Clock 0: disable, 1: enable
SDI1_CPU_1XCLKACT	11:11	800	0	0	SDIO controller 1 AMBA Clock control 0: disable, 1: enable
SPI0_CPU_1XCLKACT	14:14	4000	0	0	SPI 0 AMBA Clock control 0: disable, 1: enable
SPI1_CPU_1XCLKACT	15:15	8000	0	0	SPI 1 AMBA Clock control 0: disable, 1: enable
CAN0_CPU_1XCLKACT	16:16	10000	0	0	CAN 0 AMBA Clock control 0: disable, 1: enable
CAN1_CPU_1XCLKACT	17:17	20000	0	0	CAN 1 AMBA Clock control 0: disable, 1: enable
I2C0_CPU_1XCLKACT	18:18	40000	1	40000	I2C 0 AMBA Clock control 0: disable, 1: enable
I2C1_CPU_1XCLKACT	19:19	80000	1	80000	I2C 1 AMBA Clock control 0: disable, 1: enable
UART0_CPU_1XCLKACT	20:20	100000	1	100000	UART 0 AMBA Clock control 0: disable, 1: enable
UART1_CPU_1XCLKACT	21:21	200000	0	0	UART 1 AMBA Clock control 0: disable, 1: enable
GPIO_CPU_1XCLKACT	22:22	400000	1	400000	GPIO AMBA Clock control 0: disable, 1: enable
LQSPI_CPU_1XCLKACT	23:23	800000	1	800000	Quad SPI AMBA Clock control 0: disable, 1: enable
SMC_CPU_1XCLKACT	24:24	1000000	1	1000000	SMC AMBA Clock control 0: disable, 1: enable
APER_CLK_CTRL@0XF800012C	31:0	1ffcccd		1dc000d	AMBA Peripheral Clock Control

THIS SHOULD BE BLANK

LOCK IT BACK

Register ( slcr )SLCR_LOCK

Register Name	Address	Width	Type	Reset Value	Description
SLCR_LOCK	0XF8000004	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
LOCK_KEY	15:0	ffff	767b	767b	When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero.
SLCR_LOCK@0XF8000004	31:0	ffff		767b	SLCR Write Protection Lock

ps7_mio_init_data_2_0

Register Name	Address	Width	Type	Reset Value	Description
SLCR_UNLOCK	0XF8000008	32	WO	0x000000	SLCR Write Protection Unlock
MIO_PIN_00	0XF8000700	32	RW	0x000000	MIO Pin 0 Control
MIO_PIN_01	0XF8000704	32	RW	0x000000	MIO Pin 1 Control
MIO_PIN_02	0XF8000708	32	RW	0x000000	MIO Pin 2 Control
MIO_PIN_03	0XF800070C	32	RW	0x000000	MIO Pin 3 Control
MIO_PIN_04	0XF8000710	32	RW	0x000000	MIO Pin 4 Control
MIO_PIN_05	0XF8000714	32	RW	0x000000	MIO Pin 5 Control
MIO_PIN_06	0XF8000718	32	RW	0x000000	MIO Pin 6 Control
MIO_PIN_07	0XF800071C	32	RW	0x000000	MIO Pin 7 Control
MIO_PIN_08	0XF8000720	32	RW	0x000000	MIO Pin 8 Control
MIO_PIN_09	0XF8000724	32	RW	0x000000	MIO Pin 9 Control
MIO_PIN_10	0XF8000728	32	RW	0x000000	MIO Pin 10 Control
MIO_PIN_11	0XF800072C	32	RW	0x000000	MIO Pin 11 Control
MIO_PIN_12	0XF8000730	32	RW	0x000000	MIO Pin 12 Control
MIO_PIN_13	0XF8000734	32	RW	0x000000	MIO Pin 13 Control
MIO_PIN_14	0XF8000738	32	RW	0x000000	MIO Pin 14 Control
MIO_PIN_15	0XF800073C	32	RW	0x000000	MIO Pin 15 Control
MIO_PIN_28	0XF8000770	32	RW	0x000000	MIO Pin 28 Control
MIO_PIN_29	0XF8000774	32	RW	0x000000	MIO Pin 29 Control
MIO_PIN_30	0XF8000778	32	RW	0x000000	MIO Pin 30 Control
MIO_PIN_31	0XF800077C	32	RW	0x000000	MIO Pin 31 Control
MIO_PIN_32	0XF8000780	32	RW	0x000000	MIO Pin 32 Control
MIO_PIN_33	0XF8000784	32	RW	0x000000	MIO Pin 33 Control
MIO_PIN_34	0XF8000788	32	RW	0x000000	MIO Pin 34 Control
MIO_PIN_35	0XF800078C	32	RW	0x000000	MIO Pin 35 Control
MIO_PIN_36	0XF8000790	32	RW	0x000000	MIO Pin 36 Control
MIO_PIN_37	0XF8000794	32	RW	0x000000	MIO Pin 37 Control
MIO_PIN_38	0XF8000798	32	RW	0x000000	MIO Pin 38 Control
MIO_PIN_39	0XF800079C	32	RW	0x000000	MIO Pin 39 Control
MIO_PIN_48	0XF80007C0	32	RW	0x000000	MIO Pin 48 Control
MIO_PIN_49	0XF80007C4	32	RW	0x000000	MIO Pin 49 Control
MIO_PIN_52	0XF80007D0	32	RW	0x000000	MIO Pin 52 Control
MIO_PIN_53	0XF80007D4	32	RW	0x000000	MIO Pin 53 Control
SLCR_LOCK	0XF8000004	32	WO	0x000000	SLCR Write Protection Lock

ps7_mio_init_data_2_0

SLCR SETTINGS

Register ( slcr )SLCR_UNLOCK

Register Name

Address

Width

Type

Reset Value

Description

Register Name	Address	Width	Type	Reset Value	Description
SLCR_UNLOCK	0XF8000008	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
UNLOCK_KEY	15:0	ffff	df0d	df0d	When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero.
SLCR_UNLOCK@0XF8000008	31:0	ffff		df0d	SLCR Write Protection Unlock

OCM REMAPPING

MIO PROGRAMMING

Register ( slcr )MIO_PIN_00

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_00	0XF8000700	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Tri-state enable, active high. 0: disable 1: enable
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: reserved
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0 10: NAND Flash Chip Select 11: SDIO 0 Power Control output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 0 (bank 0) others: reserved
Speed	8:8	100	0	0	Select IO Buffer Edge Rate, applicable when IO_Type= LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge
IO_Type	11:9	e00	3	600	Select the IO Buffer Type. 000: LVTTL 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL
PULLUP	12:12	1000	1	1000	Enables pull-up on IO Buffer pin 0: disable 1: enable
DisableRcvr	13:13	2000	0	0	Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable
MIO_PIN_00@0XF8000700	31:0	3fff		1600	MIO Pin 0 Control

Register ( slcr )MIO_PIN_01

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_01	0XF8000704	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	1	2	Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: reserved
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25 10: SRAM/NOR Chip Select 1 11: SDIO 1 Power Control output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 1 (bank 0) others: reserved
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULL_UP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_01@0XF8000704	31:0	3fff		1602	MIO Pin 1 Control

Register ( slcr )MIO_PIN_02

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_02	0XF8000708	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	1	2	Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn 11: SDIO 0 Power Control output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 2 (bank 0) others: reserved
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	0	0	Operates the same as MIO_PIN_00[PULL_UP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_02@0XF8000708	31:0	3fff		602	MIO Pin 2 Control

Register ( slcr )MIO_PIN_03

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_03	0XF800070C	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	1	2	Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0 10: NAND WE_B output 11: SDIO 1 Card Power output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 3 (bank 0) others: reserved
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	0	0	Operates the same as MIO_PIN_00[PULL_UP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_03@0XF800070C	31:0	3fff		602	MIO Pin 3 Control

Register ( slcr )MIO_PIN_04

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_04	0XF8000710	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	1	2	Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1 10: NAND Flash IO Bit 2 11: SDIO 0 Power Control output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 4 (bank 0) others: reserved
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	0	0	Operates the same as MIO_PIN_00[PULL_UP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_04@0XF8000710	31:0	3fff		602	MIO Pin 4 Control

Register ( slcr )MIO_PIN_05

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_05	0XF8000714	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	1	2	Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2 10: NAND Flash IO Bit 0 11: SDIO 1 Power Control output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 5 (bank 0) others: reserved
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	0	0	Operates the same as MIO_PIN_00[PULL_UP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_05@0XF8000714	31:0	3fff		602	MIO Pin 5 Control

Register ( slcr )MIO_PIN_06

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_06	0XF8000718	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	1	2	Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock Output
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3 10: NAND Flash IO Bit 1 11: SDIO 0 Power Control output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 6 (bank 0) others: reserved
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	0	0	Operates the same as MIO_PIN_00[PULL_UP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_06@0XF8000718	31:0	3fff		602	MIO Pin 6 Control

Register ( slcr )MIO_PIN_07

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_07	0XF800071C	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: reserved
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B 10: NAND Flash CLE_B 11: SDIO 1 Power Control output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 7 Output-only (bank 0) others: reserved
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	0	0	Operates the same as MIO_PIN_00[PULL_UP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_07@0XF800071C	31:0	3fff		600	MIO Pin 7 Control

Register ( slcr )MIO_PIN_08

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_08	0XF8000720	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Output Clock
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR WE_B 10: NAND Flash RD_B 11: SDIO 0 Power Control output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 8 Output-only (bank 0) 001: CAN 1 Tx 010: sram, Output, smc_sram_bls_b 011 to 110: reserved 111: UART 1 TxD
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	0	0	Operates the same as MIO_PIN_00[PULL_UP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_08@0XF8000720	31:0	3fff		600	MIO Pin 8 Control

Register ( slcr )MIO_PIN_09

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_09	0XF8000724	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock Output
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6 10: NAND Flash IO Bit 4 11: SDIO 1 Power Control output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 9 (bank 0) 001: CAN 1 Rx 010 to 110: reserved 111: UART 1 RxD
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULL_UP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_09@0XF8000724	31:0	3fff		1600	MIO Pin 9 Control

Register ( slcr )MIO_PIN_10

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_10	0XF8000728	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7 10: NAND Flash IO Bit 5 11: SDIO 0 Power Control output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 10 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULL_UP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_10@0XF8000728	31:0	3fff		1600	MIO Pin 10 Control

Register ( slcr )MIO_PIN_11

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_11	0XF800072C	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4 10: NAND Flash IO Bit 6 11: SDIO 1 Power Control output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 11 (bank 0) 001: CAN 0 Tx 010: I2C Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULL_UP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_11@0XF800072C	31:0	3fff		1600	MIO Pin 11 Control

Register ( slcr )MIO_PIN_12

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_12	0XF8000730	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait 10: NAND Flash IO Bit 7 11: SDIO 0 Power Control output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 12 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULL_UP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_12@0XF8000730	31:0	3fff		1600	MIO Pin 12 Control

Register ( slcr )MIO_PIN_13

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_13	0XF8000734	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5 10: NAND Flash IO Bit 3 11: SDIO 1 Power Control output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 13 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULL_UP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_13@0XF8000734	31:0	3fff		1600	MIO Pin 13 Control

Register ( slcr )MIO_PIN_14

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_14	0XF8000738	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1= Not Used
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy 11: SDIO 0 Power Control output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 14 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 slave select 1 110: reserved 111: UART 0 RxD
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULL_UP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_14@0XF8000738	31:0	3fff		1600	MIO Pin 14 Control

Register ( slcr )MIO_PIN_15

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_15	0XF800073C	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1= Not Used
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0 10: reserved 11: SDIO 1 Power Control output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 15 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULL_UP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_15@0XF800073C	31:0	3fff		1600	MIO Pin 15 Control

Register ( slcr )MIO_PIN_28

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_28	0XF8000770	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13 10: reserved 11: SDIO 0 Power Control output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 28 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULL_UP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_28@0XF8000770	31:0	3fff		1600	MIO Pin 28 Control

Register ( slcr )MIO_PIN_29

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_29	0XF8000774	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14 10: reserved 11: SDIO 1 Power Control output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 29 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULL_UP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_29@0XF8000774	31:0	3fff		1600	MIO Pin 29 Control

Register ( slcr )MIO_PIN_30

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_30	0XF8000778	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15 10: reserved 11: SDIO 0 Power Control output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 30 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULL_UP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_30@0XF8000778	31:0	3fff		1600	MIO Pin 30 Control

Register ( slcr )MIO_PIN_31

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_31	0XF800077C	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16 10: reserved 11: SDIO 1 Power Control output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 31 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULL_UP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_31@0XF800077C	31:0	3fff		1600	MIO Pin 31 Control

Register ( slcr )MIO_PIN_32

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_32	0XF8000780	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17 10: reserved 11: SDIO 0 Power Control output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 32 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULL_UP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_32@0XF8000780	31:0	3fff		1600	MIO Pin 32 Control

Register ( slcr )MIO_PIN_33

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_33	0XF8000784	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18 10: reserved 11: SDIO 1 Power Control output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 33 (Bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULL_UP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_33@0XF8000784	31:0	3fff		1600	MIO Pin 33 Control

Register ( slcr )MIO_PIN_34

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_34	0XF8000788	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19 10: reserved 11: SDIO 0 Power Control output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 34 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 110: reserved 111: UART 0 RxD
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULL_UP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_34@0XF8000788	31:0	3fff		1600	MIO Pin 34 Control

Register ( slcr )MIO_PIN_35

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_35	0XF800078C	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20 10: reserved 11: SDIO 1 Power Control output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 35 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 Command 110: reserved 111: UART 0 TxD
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULL_UP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_35@0XF800078C	31:0	3fff		1600	MIO Pin 35 Control

Register ( slcr )MIO_PIN_36

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_36	0XF8000790	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21 10: reserved 11: SDIO 0 Power Control output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 36 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Clock 110: reserved 111: UART 1 TxD
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULL_UP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_36@0XF8000790	31:0	3fff		1600	MIO Pin 36 Control

Register ( slcr )MIO_PIN_37

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_37	0XF8000794	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22 10: reserved 11: SDIO 1 Power Control output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 37 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS+H2129 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULL_UP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_37@0XF8000794	31:0	3fff		1600	MIO Pin 37 Control

Register ( slcr )MIO_PIN_38

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_38	0XF8000798	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23 10: reserved 11: SDIO 0 Power Control output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 38 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock In 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULL_UP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_38@0XF8000798	31:0	3fff		1600	MIO Pin 38 Control

Register ( slcr )MIO_PIN_39

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_39	0XF800079C	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24 10: reserved 11: SDIO 1 Power Control output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 39 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULL_UP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_39@0XF800079C	31:0	3fff		1600	MIO Pin 39 Control

Register ( slcr )MIO_PIN_48

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_48	0XF80007C0	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: reserved
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 48 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULL_UP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_48@0XF80007C0	31:0	3fff		1600	MIO Pin 48 Control

Register ( slcr )MIO_PIN_49

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_49	0XF80007C4	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: reserved
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 49 (bank 1) 001: CAN 1 Rx 010: I2C Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Select 0 110: reserved 111: UART 1 RxD
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULL_UP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_49@0XF80007C4	31:0	3fff		1600	MIO Pin 49 Control

Register ( slcr )MIO_PIN_52

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_52	0XF80007D0	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: reserved
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: reserved
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 52 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: SWDT Clock Input 100: MDIO 0 Clock 101: MDIO 1 Clock 110: reserved 111: UART 1 TxD
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULL_UP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_52@0XF80007D0	31:0	3fff		1600	MIO Pin 52 Control

Register ( slcr )MIO_PIN_53

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_53	0XF80007D4	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Operates the same as MIO_PIN_00[TRI_ENABLE]
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0: Level 1 Mux 1: reserved
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0: Level 2 Mux 1: reserved
L2_SEL	4:3	18	0	0	Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 000: GPIO 53 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: SWDT Reset Output 100: MDIO 0 Data 101: MDIO 1 Data 110: reserved 111: UART 1 RxD
Speed	8:8	100	0	0	Operates the same as MIO_PIN_00[Speed]
IO_Type	11:9	e00	3	600	Operates the same as MIO_PIN_00[IO_Type]
PULLUP	12:12	1000	1	1000	Operates the same as MIO_PIN_00[PULL_UP]
DisableRcvr	13:13	2000	0	0	Operates the same as MIO_PIN_00[DisableRcvr]
MIO_PIN_53@0XF80007D4	31:0	3fff		1600	MIO Pin 53 Control

LOCK IT BACK

Register ( slcr )SLCR_LOCK

Register Name	Address	Width	Type	Reset Value	Description
SLCR_LOCK	0XF8000004	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
LOCK_KEY	15:0	ffff	767b	767b	When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero.
SLCR_LOCK@0XF8000004	31:0	ffff		767b	SLCR Write Protection Lock

ps7_peripherals_init_data_2_0

Register Name	Address	Width	Type	Reset Value	Description
SLCR_UNLOCK	0XF8000008	32	WO	0x000000	SLCR Write Protection Unlock
SLCR_LOCK	0XF8000004	32	WO	0x000000	SLCR Write Protection Lock
Baud_rate_divider_reg0	0XE0000034	32	RW	0x000000	baud rate divider register
Baud_rate_gen_reg0	0XE0000018	32	RW	0x000000	Baud rate divider register.
Control_reg0	0XE0000000	32	RW	0x000000	UART Control register
mode_reg0	0XE0000004	32	RW	0x000000	UART Mode register
Config_reg	0XE000D000	32	RW	0x000000	SPI configuration register
CTRL	0XF8007000	32	RW	0x000000	Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.

ps7_peripherals_init_data_2_0

SLCR SETTINGS

Register ( slcr )SLCR_UNLOCK

Register Name

Address

Width

Type

Reset Value

Description

Register Name	Address	Width	Type	Reset Value	Description
SLCR_UNLOCK	0XF8000008	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
UNLOCK_KEY	15:0	ffff	df0d	df0d	When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero.
SLCR_UNLOCK@0XF8000008	31:0	ffff		df0d	SLCR Write Protection Unlock

LOCK IT BACK

Register ( slcr )SLCR_LOCK

Register Name	Address	Width	Type	Reset Value	Description
SLCR_LOCK	0XF8000004	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
LOCK_KEY	15:0	ffff	767b	767b	When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero.
SLCR_LOCK@0XF8000004	31:0	ffff		767b	SLCR Write Protection Lock

SRAM/NOR SET OPMODE

UART REGISTERS

Register ( slcr )Baud_rate_divider_reg0

Register Name	Address	Width	Type	Reset Value	Description
Baud_rate_divider_reg0	0XE0000034	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
BDIV	7:0	ff	6	6	Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
Baud_rate_divider_reg0@0XE0000034	31:0	ff		6	baud rate divider register

Register ( slcr )Baud_rate_gen_reg0

Register Name	Address	Width	Type	Reset Value	Description
Baud_rate_gen_reg0	0XE0000018	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
CD	15:0	ffff	7c	7c	Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass 2 - 65535: baud_sample value
Baud_rate_gen_reg0@0XE0000018	31:0	ffff		7c	Baud rate divider register.

Register ( slcr )Control_reg0

Register Name	Address	Width	Type	Reset Value	Description
Control_reg0	0XE0000000	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
STPBRK	8:8	100	0	0	Stop transmitter break: 0: start break transmission, 1: stop break transmission.
STTBRK	7:7	80	0	0	Start transmitter break: 0: 1: start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high.
RSTTO	6:6	40	0	0	Restart receiver timeout counter: 0: receiver timeout counter disabled, 1: receiver timeout counter is restarted.
TXDIS	5:5	20	0	0	Transmit disable: 0: enable transmitter, 0: disable transmitter
TXEN	4:4	10	1	10	Transmit enable: 0: disable transmitter, 1: enable transmitter, provided the TXDIS field is set to 0.
RXDIS	3:3	8	0	0	Receive disable: 0: disable, 1: enable
RXEN	2:2	4	1	4	Receive enable: 0: disable, 1: enable. When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.
TXRES	1:1	2	1	2	Software reset for Tx data path: 0: 1: transmitter logic is reset and all pending transmitter data is discarded self clear
RXRES	0:0	1	1	1	Software reset for Rx data path: 0: 1: receiver logic is reset and all pending receiver data is discarded self clear
Control_reg0@0XE0000000	31:0	1ff		17	UART Control register

Register ( slcr )mode_reg0

Register Name	Address	Width	Type	Reset Value	Description
mode_reg0	0XE0000004	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
IRMODE	11:11	800	0	0	Enable IrDA mode: 0: Default UART mode 1: Enable IrDA mode
UCLKEN	10:10	400	0	0	External uart_clk source select: 0: APB clock, pclk 1: a user-defined clock
CHMODE	9:8	300	0	0	Channel mode: 00: normal 01: automatic cho 10: local loopback 11: remote loopback
NBSTOP	7:6	c0	0	0	Number of stop bits: 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved
PAR	5:3	38	4	20	Parity type select: 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity
CHRL	2:1	6	0	0	Character length select: 11: 6 bits 10: 7 bits 0x: 8 bits
CLKS	0:0	1	0	0	Clock source select: 0: clock source is uart_clk 1: clock source is uart_clk/8
mode_reg0@0XE0000004	31:0	fff		20	UART Mode register

QSPI REGISTERS

Register ( slcr )Config_reg

Register Name	Address	Width	Type	Reset Value	Description
Config_reg	0XE000D000	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
Holdb_dr	19:19	80000	1	80000	Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode.
Config_reg@0XE000D000	31:0	80000		80000	SPI configuration register

PL POWER ON RESET REGISTERS

Register ( slcr )CTRL

Register Name	Address	Width	Type	Reset Value	Description
CTRL	0XF8007000	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PCFG_POR_CNT_4K	29:29	20000000	0	0	This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer
CTRL@0XF8007000	31:0	20000000		0	Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.

SMC TIMING CALCULATION REGISTER UPDATE

NAND SET CYCLE

OPMODE

DIRECT COMMAND

SRAM/NOR CS0 SET CYCLE

DIRECT COMMAND

NOR CS0 BASE ADDRESS

SRAM/NOR CS1 SET CYCLE

DIRECT COMMAND

NOR CS1 BASE ADDRESS

USB RESET

ENET RESET

I2C RESET

NOR CHIP SELECT

DIR MODE BANK 0

MASK_DATA_0_LSW HIGH BANK [15:0]

OUTPUT ENABLE BANK 0

ps7_post_config_2_0

Register Name	Address	Width	Type	Reset Value	Description
SLCR_UNLOCK	0XF8000008	32	WO	0x000000	SLCR Write Protection Unlock
LVL_SHFTR_EN	0XF8000900	32	RW	0x000000	Level Shifters Enable
FPGA_RST_CTRL	0XF8000240	32	RW	0x000000	FPGA Software Reset Control
SLCR_LOCK	0XF8000004	32	WO	0x000000	SLCR Write Protection Lock

ps7_post_config_2_0

SLCR SETTINGS

Register ( slcr )SLCR_UNLOCK

Register Name

Address

Width

Type

Reset Value

Description

Register Name	Address	Width	Type	Reset Value	Description
SLCR_UNLOCK	0XF8000008	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
UNLOCK_KEY	15:0	ffff	df0d	df0d	When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero.
SLCR_UNLOCK@0XF8000008	31:0	ffff		df0d	SLCR Write Protection Unlock

ENABLING LEVEL SHIFTER

Register ( slcr )LVL_SHFTR_EN

Register Name	Address	Width	Type	Reset Value	Description
LVL_SHFTR_EN	0XF8000900	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
USER_INP_ICT_EN_0	1:0	3	3	3	Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0].
USER_INP_ICT_EN_1	3:2	c	3	c	Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0].
LVL_SHFTR_EN@0XF8000900	31:0	f		f	Level Shifters Enable

FPGA RESETS TO 0

Register ( slcr )FPGA_RST_CTRL

Register Name	Address	Width	Type	Reset Value	Description
FPGA_RST_CTRL	0XF8000240	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
reserved_3	31:25	fe000000	0	0	Reserved. Writes are ignored, read data is zero.
FPGA_ACP_RST	24:24	1000000	0	0	FPGA ACP port soft reset: 0: No reset 1: ACP AXI interface reset output asserted
FPGA_AXDS3_RST	23:23	800000	0	0	AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0: No reset 1: AXDS3AXI interface reset output asserted
FPGA_AXDS2_RST	22:22	400000	0	0	AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0: No reset 1: AXDS2 AXI interface reset output asserted
FPGA_AXDS1_RST	21:21	200000	0	0	AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0: No reset 1: AXDS1 AXI interface reset output asserted
FPGA_AXDS0_RST	20:20	100000	0	0	AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0: No reset 1: AXDS0 AXI interface reset output asserted
reserved_2	19:18	c0000	0	0	Reserved. Writes are ignored, read data is zero.
FSSW1_FPGA_RST	17:17	20000	0	0	General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0: No reset 1: FPGA slave interface 1 reset is asserted
FSSW0_FPGA_RST	16:16	10000	0	0	General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0: No reset 1: FPGA slave interface 0 reset is asserted
reserved_1	15:14	c000	0	0	Reserved. Writes are ignored, read data is zero.
FPGA_FMSW1_RST	13:13	2000	0	0	General purpose FPGA master interface: 1: soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0: No reset 1: FPGA master interface 1 reset is asserted
FPGA_FMSW0_RST	12:12	1000	0	0	General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0: No reset 1: FPGA master interface 0 reset is asserted.
FPGA_DMA3_RST	11:11	800	0	0	FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 3 peripheral request reset output asserted
FPGA_DMA2_RST	10:10	400	0	0	FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 2 peripheral request reset output asserted
FPGA_DMA1_RST	9:9	200	0	0	FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 1 peripheral request reset output asserted
FPGA_DMA0_RST	8:8	100	0	0	FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 0 peripheral request reset output asserted
reserved	7:4	f0	0	0	Reserved. Writes are ignored, read data is zero.
FPGA3_OUT_RST	3:3	8	0	0	FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0: No reset 1: FPGA 3 top level reset output asserted
FPGA2_OUT_RST	2:2	4	0	0	FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0: No reset 1: FPGA 2 top level reset output asserted
FPGA1_OUT_RST	1:1	2	0	0	FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0: No reset 1: FPGA 1 top level reset output asserted
FPGA0_OUT_RST	0:0	1	0	0	FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0: No reset 1: FPGA 0 top level reset output asserted
FPGA_RST_CTRL@0XF8000240	31:0	ffffffff		0	FPGA Software Reset Control

AFI REGISTERS

AFI0 REGISTERS

AFI1 REGISTERS

AFI2 REGISTERS

AFI3 REGISTERS

LOCK IT BACK

Register ( slcr )SLCR_LOCK

Register Name	Address	Width	Type	Reset Value	Description
SLCR_LOCK	0XF8000004	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
LOCK_KEY	15:0	ffff	767b	767b	When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero.
SLCR_LOCK@0XF8000004	31:0	ffff		767b	SLCR Write Protection Lock

ps7_debug_2_0

Register Name	Address	Width	Type	Reset Value	Description
LAR	0XF8898FB0	32	WO	0x000000	Lock Access Register
LAR	0XF8899FB0	32	WO	0x000000	Lock Access Register
LAR	0XF8809FB0	32	WO	0x000000	Lock Access Register

ps7_debug_2_0

CROSS TRIGGER CONFIGURATIONS

UNLOCKING CTI REGISTERS

Register ( slcr )LAR

Register Name

Address

Width

Type

Reset Value

Description

Register Name	Address	Width	Type	Reset Value	Description
LAR	0XF8898FB0	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
KEY	31:0	ffffffff	c5acce55	c5acce55	Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.
LAR@0XF8898FB0	31:0	ffffffff		c5acce55	Lock Access Register

Register ( slcr )LAR

Register Name	Address	Width	Type	Reset Value	Description
LAR	0XF8899FB0	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
KEY	31:0	ffffffff	c5acce55	c5acce55	Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.
LAR@0XF8899FB0	31:0	ffffffff		c5acce55	Lock Access Register

Register ( slcr )LAR

Register Name	Address	Width	Type	Reset Value	Description
LAR	0XF8809FB0	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
KEY	31:0	ffffffff	c5acce55	c5acce55	Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.
LAR@0XF8809FB0	31:0	ffffffff		c5acce55	Lock Access Register

ENABLING CTI MODULES AND CHANNELS

MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

ps7_pll_init_data_1_0

Register Name	Address	Width	Type	Reset Value	Description
SLCR_UNLOCK	0XF8000008	32	WO	0x000000	SLCR Write Protection Unlock
ARM_PLL_CFG	0XF8000110	32	RW	0x000000	ARM PLL Configuration
ARM_PLL_CTRL	0XF8000100	32	RW	0x000000	ARM PLL Control
ARM_PLL_CTRL	0XF8000100	32	RW	0x000000	ARM PLL Control
ARM_PLL_CTRL	0XF8000100	32	RW	0x000000	ARM PLL Control
ARM_PLL_CTRL	0XF8000100	32	RW	0x000000	ARM PLL Control
ARM_PLL_CTRL	0XF8000100	32	RW	0x000000	ARM PLL Control
ARM_CLK_CTRL	0XF8000120	32	RW	0x000000	CORTEX A9 Clock Control
DDR_PLL_CFG	0XF8000114	32	RW	0x000000	DDR PLL Configuration
DDR_PLL_CTRL	0XF8000104	32	RW	0x000000	DDR PLL Control
DDR_PLL_CTRL	0XF8000104	32	RW	0x000000	DDR PLL Control
DDR_PLL_CTRL	0XF8000104	32	RW	0x000000	DDR PLL Control
DDR_PLL_CTRL	0XF8000104	32	RW	0x000000	DDR PLL Control
DDR_PLL_CTRL	0XF8000104	32	RW	0x000000	DDR PLL Control
DDR_CLK_CTRL	0XF8000124	32	RW	0x000000	DDR Clock Control
IO_PLL_CFG	0XF8000118	32	RW	0x000000	IO PLL Configuration
IO_PLL_CTRL	0XF8000108	32	RW	0x000000	IO PLL Control
IO_PLL_CTRL	0XF8000108	32	RW	0x000000	IO PLL Control
IO_PLL_CTRL	0XF8000108	32	RW	0x000000	IO PLL Control
IO_PLL_CTRL	0XF8000108	32	RW	0x000000	IO PLL Control
IO_PLL_CTRL	0XF8000108	32	RW	0x000000	IO PLL Control
SLCR_LOCK	0XF8000004	32	WO	0x000000	SLCR Write Protection Lock

ps7_pll_init_data_1_0

SLCR SETTINGS

Register ( slcr )SLCR_UNLOCK

Register Name

Address

Width

Type

Reset Value

Description

Register Name	Address	Width	Type	Reset Value	Description
SLCR_UNLOCK	0XF8000008	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
UNLOCK_KEY	15:0	ffff	df0d	df0d	When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero.
SLCR_UNLOCK@0XF8000008	31:0	ffff		df0d	SLCR Write Protection Unlock

PLL SLCR REGISTERS

ARM PLL INIT

Register ( slcr )ARM_PLL_CFG

Register Name	Address	Width	Type	Reset Value	Description
ARM_PLL_CFG	0XF8000110	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_RES	7:4	f0	2	20	Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control
PLL_CP	11:8	f00	2	200	Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control
LOCK_CNT	21:12	3ff000	fa	fa000	Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked.
ARM_PLL_CFG@0XF8000110	31:0	3ffff0		fa220	ARM PLL Configuration

UPDATE FB_DIV

Register ( slcr )ARM_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
ARM_PLL_CTRL	0XF8000100	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_FDIV	18:12	7f000	28	28000	Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state.
ARM_PLL_CTRL@0XF8000100	31:0	7f000		28000	ARM PLL Control

BY PASS PLL

Register ( slcr )ARM_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
ARM_PLL_CTRL	0XF8000100	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_BYPASS_FORCE	4:4	10	1	10	Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed.
ARM_PLL_CTRL@0XF8000100	31:0	10		10	ARM PLL Control

ASSERT RESET

Register ( slcr )ARM_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
ARM_PLL_CTRL	0XF8000100	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_RESET	0:0	1	1	1	Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.
ARM_PLL_CTRL@0XF8000100	31:0	1		1	ARM PLL Control

DEASSERT RESET

Register ( slcr )ARM_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
ARM_PLL_CTRL	0XF8000100	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_RESET	0:0	1	0	0	Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.
ARM_PLL_CTRL@0XF8000100	31:0	1		0	ARM PLL Control

CHECK PLL STATUS

Register ( slcr )PLL_STATUS

Register Name	Address	Width	Type	Reset Value	Description
PLL_STATUS	0XF800010C	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
ARM_PLL_LOCK	0:0	1	1	1	ARM PLL lock status. 0 - ARM PLL out of lock. 1 - ARM PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used.
PLL_STATUS@0XF800010C	31:0	1		1	tobe

REMOVE PLL BY PASS

Register ( slcr )ARM_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
ARM_PLL_CTRL	0XF8000100	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_BYPASS_FORCE	4:4	10	0	0	Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed.
ARM_PLL_CTRL@0XF8000100	31:0	10		0	ARM PLL Control

Register ( slcr )ARM_CLK_CTRL

Register Name	Address	Width	Type	Reset Value	Description
ARM_CLK_CTRL	0XF8000120	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
SRCSEL	5:4	30	0	0	Selects the source used to generate the clock. 0x - Source for generated clock is CPU PLL. 10 - Source for generated clock is DDR divided clock. 11 - Source for generated clock is IO PLL
DIVISOR	13:8	3f00	2	200	Provides the divisor used to divide the source clock to generate the required generated clock frequency.
CPU_6OR4XCLKACT	24:24	1000000	1	1000000	Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
CPU_3OR2XCLKACT	25:25	2000000	1	2000000	Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
CPU_2XCLKACT	26:26	4000000	1	4000000	Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
CPU_1XCLKACT	27:27	8000000	1	8000000	Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
CPU_PERI_CLKACT	28:28	10000000	1	10000000	Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
ARM_CLK_CTRL@0XF8000120	31:0	1f003f30		1f000200	CORTEX A9 Clock Control

DDR PLL INIT

Register ( slcr )DDR_PLL_CFG

Register Name	Address	Width	Type	Reset Value	Description
DDR_PLL_CFG	0XF8000114	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_RES	7:4	f0	2	20	Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control
PLL_CP	11:8	f00	2	200	Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control
LOCK_CNT	21:12	3ff000	12c	12c000	Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked.
DDR_PLL_CFG@0XF8000114	31:0	3ffff0		12c220	DDR PLL Configuration

UPDATE FB_DIV

Register ( slcr )DDR_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
DDR_PLL_CTRL	0XF8000104	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_FDIV	18:12	7f000	20	20000	Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state.
DDR_PLL_CTRL@0XF8000104	31:0	7f000		20000	DDR PLL Control

BY PASS PLL

Register ( slcr )DDR_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
DDR_PLL_CTRL	0XF8000104	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_BYPASS_FORCE	4:4	10	1	10	Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed
DDR_PLL_CTRL@0XF8000104	31:0	10		10	DDR PLL Control

ASSERT RESET

Register ( slcr )DDR_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
DDR_PLL_CTRL	0XF8000104	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_RESET	0:0	1	1	1	Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.
DDR_PLL_CTRL@0XF8000104	31:0	1		1	DDR PLL Control

DEASSERT RESET

Register ( slcr )DDR_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
DDR_PLL_CTRL	0XF8000104	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_RESET	0:0	1	0	0	Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.
DDR_PLL_CTRL@0XF8000104	31:0	1		0	DDR PLL Control

CHECK PLL STATUS

Register ( slcr )PLL_STATUS

Register Name	Address	Width	Type	Reset Value	Description
PLL_STATUS	0XF800010C	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
DDR_PLL_LOCK	1:1	2	1	2	DDR PLL lock status. 0 - DDR PLL out of lock. 1 - DDR PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used.
PLL_STATUS@0XF800010C	31:0	2		2	tobe

REMOVE PLL BY PASS

Register ( slcr )DDR_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
DDR_PLL_CTRL	0XF8000104	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_BYPASS_FORCE	4:4	10	0	0	Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed
DDR_PLL_CTRL@0XF8000104	31:0	10		0	DDR PLL Control

Register ( slcr )DDR_CLK_CTRL

Register Name	Address	Width	Type	Reset Value	Description
DDR_CLK_CTRL	0XF8000124	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
DDR_3XCLKACT	0:0	1	1	1	Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
DDR_2XCLKACT	1:1	2	1	2	Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
DDR_3XCLK_DIVISOR	25:20	3f00000	2	200000	Divisor value for the ddr_3xclk
DDR_2XCLK_DIVISOR	31:26	fc000000	3	c000000	Divisor value for the ddr_2xclk (does not have to be 2/3 speed of ddr_3xclk)
DDR_CLK_CTRL@0XF8000124	31:0	fff00003		c200003	DDR Clock Control

IO PLL INIT

Register ( slcr )IO_PLL_CFG

Register Name	Address	Width	Type	Reset Value	Description
IO_PLL_CFG	0XF8000118	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_RES	7:4	f0	4	40	Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control
PLL_CP	11:8	f00	2	200	Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control
LOCK_CNT	21:12	3ff000	fa	fa000	Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked.
IO_PLL_CFG@0XF8000118	31:0	3ffff0		fa240	IO PLL Configuration

UPDATE FB_DIV

Register ( slcr )IO_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
IO_PLL_CTRL	0XF8000108	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_FDIV	18:12	7f000	30	30000	Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state.
IO_PLL_CTRL@0XF8000108	31:0	7f000		30000	IO PLL Control

BY PASS PLL

Register ( slcr )IO_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
IO_PLL_CTRL	0XF8000108	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_BYPASS_FORCE	4:4	10	1	10	Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed
IO_PLL_CTRL@0XF8000108	31:0	10		10	IO PLL Control

ASSERT RESET

Register ( slcr )IO_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
IO_PLL_CTRL	0XF8000108	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_RESET	0:0	1	1	1	Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.
IO_PLL_CTRL@0XF8000108	31:0	1		1	IO PLL Control

DEASSERT RESET

Register ( slcr )IO_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
IO_PLL_CTRL	0XF8000108	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_RESET	0:0	1	0	0	Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.
IO_PLL_CTRL@0XF8000108	31:0	1		0	IO PLL Control

CHECK PLL STATUS

Register ( slcr )PLL_STATUS

Register Name	Address	Width	Type	Reset Value	Description
PLL_STATUS	0XF800010C	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
IO_PLL_LOCK	2:2	4	1	4	IO PLL lock status. 0 - IO PLL out of lock. 1 - IO PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used.
PLL_STATUS@0XF800010C	31:0	4		4	tobe

REMOVE PLL BY PASS

Register ( slcr )IO_PLL_CTRL

Register Name	Address	Width	Type	Reset Value	Description
IO_PLL_CTRL	0XF8000108	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PLL_BYPASS_FORCE	4:4	10	0	0	Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed
IO_PLL_CTRL@0XF8000108	31:0	10		0	IO PLL Control

LOCK IT BACK

Register ( slcr )SLCR_LOCK

Register Name	Address	Width	Type	Reset Value	Description
SLCR_LOCK	0XF8000004	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
LOCK_KEY	15:0	ffff	767b	767b	When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero.
SLCR_LOCK@0XF8000004	31:0	ffff		767b	SLCR Write Protection Lock

ps7_clock_init_data_1_0

Register Name	Address	Width	Type	Reset Value	Description
SLCR_UNLOCK	0XF8000008	32	WO	0x000000	SLCR Write Protection Unlock
DCI_CLK_CTRL	0XF8000128	32	RW	0x000000	DCI clock control
LQSPI_CLK_CTRL	0XF800014C	32	RW	0x000000	Linear Quad-SPI Reference Clock Control
UART_CLK_CTRL	0XF8000154	32	RW	0x000000	UART Reference Clock Control
PCAP_CLK_CTRL	0XF8000168	32	RW	0x000000	PCAP 2X Clock Contol
FPGA0_CLK_CTRL	0XF8000170	32	RW	0x000000	FPGA 0 Output Clock Control
CLK_621_TRUE	0XF80001C4	32	RW	0x000000	6:2:1 ratio clock, if set
APER_CLK_CTRL	0XF800012C	32	RW	0x000000	AMBA Peripheral Clock Control
SLCR_LOCK	0XF8000004	32	WO	0x000000	SLCR Write Protection Lock

ps7_clock_init_data_1_0

SLCR SETTINGS

Register ( slcr )SLCR_UNLOCK

Register Name

Address

Width

Type

Reset Value

Description

Register Name	Address	Width	Type	Reset Value	Description
SLCR_UNLOCK	0XF8000008	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
UNLOCK_KEY	15:0	ffff	df0d	df0d	When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero.
SLCR_UNLOCK@0XF8000008	31:0	ffff		df0d	SLCR Write Protection Unlock

CLOCK CONTROL SLCR REGISTERS

Register ( slcr )DCI_CLK_CTRL

Register Name	Address	Width	Type	Reset Value	Description
DCI_CLK_CTRL	0XF8000128	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
CLKACT	0:0	1	1	1	Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
DIVISOR0	13:8	3f00	f	f00	Provides the divisor used to divide the source clock to generate the required generated clock frequency.
DIVISOR1	25:20	3f00000	7	700000	Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider
DCI_CLK_CTRL@0XF8000128	31:0	3f03f01		700f01	DCI clock control

Register ( slcr )LQSPI_CLK_CTRL

Register Name	Address	Width	Type	Reset Value	Description
LQSPI_CLK_CTRL	0XF800014C	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
CLKACT	0:0	1	1	1	Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
SRCSEL	5:4	30	0	0	Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL.
DIVISOR	13:8	3f00	8	800	Provides the divisor used to divide the source clock to generate the required generated clock frequency.
LQSPI_CLK_CTRL@0XF800014C	31:0	3f31		801	Linear Quad-SPI Reference Clock Control

Register ( slcr )UART_CLK_CTRL

Register Name	Address	Width	Type	Reset Value	Description
UART_CLK_CTRL	0XF8000154	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
CLKACT0	0:0	1	1	1	UART 0 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled.
CLKACT1	1:1	2	0	0	UART 1 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled.
SRCSEL	5:4	30	0	0	Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL.
DIVISOR	13:8	3f00	10	1000	Provides the divisor used to divide the source clock to generate the required generated clock frequency.
UART_CLK_CTRL@0XF8000154	31:0	3f33		1001	UART Reference Clock Control

TRACE CLOCK

Register ( slcr )PCAP_CLK_CTRL

Register Name	Address	Width	Type	Reset Value	Description
PCAP_CLK_CTRL	0XF8000168	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
CLKACT	0:0	1	1	1	Clock active 0 - Clock is disabled 1 - Clock is enabled
SRCSEL	5:4	30	0	0	Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL
DIVISOR	13:8	3f00	8	800	Provides the divisor used to divide the source clock to generate the required generated clock frequency.
PCAP_CLK_CTRL@0XF8000168	31:0	3f31		801	PCAP 2X Clock Contol

Register ( slcr )FPGA0_CLK_CTRL

Register Name	Address	Width	Type	Reset Value	Description
FPGA0_CLK_CTRL	0XF8000170	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
SRCSEL	5:4	30	0	0	Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL.
DIVISOR0	13:8	3f00	8	800	Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider
DIVISOR1	25:20	3f00000	4	400000	Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider
FPGA0_CLK_CTRL@0XF8000170	31:0	3f03f30		400800	FPGA 0 Output Clock Control

Register ( slcr )CLK_621_TRUE

Register Name	Address	Width	Type	Reset Value	Description
CLK_621_TRUE	0XF80001C4	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
CLK_621_TRUE	0:0	1	1	1	Enable the 6:2:1 mode. 1 for 6:3:2:1. 0 for 4:2:2:1.
CLK_621_TRUE@0XF80001C4	31:0	1		1	6:2:1 ratio clock, if set

Register ( slcr )APER_CLK_CTRL

Register Name	Address	Width	Type	Reset Value	Description
APER_CLK_CTRL	0XF800012C	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
DMA_CPU_2XCLKACT	0:0	1	1	1	DMA 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
USB0_CPU_1XCLKACT	2:2	4	1	4	USB 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
USB1_CPU_1XCLKACT	3:3	8	1	8	USB 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
GEM0_CPU_1XCLKACT	6:6	40	0	0	Gigabit Ethernet MAC 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
GEM1_CPU_1XCLKACT	7:7	80	0	0	Gigabit Ethernet MAC 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
SDI0_CPU_1XCLKACT	10:10	400	0	0	SDIO0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
SDI1_CPU_1XCLKACT	11:11	800	0	0	SDIO 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
SPI0_CPU_1XCLKACT	14:14	4000	0	0	SPI 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
SPI1_CPU_1XCLKACT	15:15	8000	0	0	SPI 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
CAN0_CPU_1XCLKACT	16:16	10000	0	0	CAN 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
CAN1_CPU_1XCLKACT	17:17	20000	0	0	CAN 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
I2C0_CPU_1XCLKACT	18:18	40000	1	40000	I2C 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
I2C1_CPU_1XCLKACT	19:19	80000	1	80000	I2C 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
UART0_CPU_1XCLKACT	20:20	100000	1	100000	UART 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
UART1_CPU_1XCLKACT	21:21	200000	0	0	UART 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
GPIO_CPU_1XCLKACT	22:22	400000	1	400000	GPIO AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
LQSPI_CPU_1XCLKACT	23:23	800000	1	800000	LQSPI AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
SMC_CPU_1XCLKACT	24:24	1000000	1	1000000	SMC AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
APER_CLK_CTRL@0XF800012C	31:0	1ffcccd		1dc000d	AMBA Peripheral Clock Control

THIS SHOULD BE BLANK

LOCK IT BACK

Register ( slcr )SLCR_LOCK

Register Name	Address	Width	Type	Reset Value	Description
SLCR_LOCK	0XF8000004	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
LOCK_KEY	15:0	ffff	767b	767b	When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero.
SLCR_LOCK@0XF8000004	31:0	ffff		767b	SLCR Write Protection Lock

ps7_mio_init_data_1_0

Register Name	Address	Width	Type	Reset Value	Description
SLCR_UNLOCK	0XF8000008	32	WO	0x000000	SLCR Write Protection Unlock
MIO_PIN_00	0XF8000700	32	RW	0x000000	MIO Control for Pin 0
MIO_PIN_01	0XF8000704	32	RW	0x000000	MIO Control for Pin 1
MIO_PIN_02	0XF8000708	32	RW	0x000000	MIO Control for Pin 2
MIO_PIN_03	0XF800070C	32	RW	0x000000	MIO Control for Pin 3
MIO_PIN_04	0XF8000710	32	RW	0x000000	MIO Control for Pin 4
MIO_PIN_05	0XF8000714	32	RW	0x000000	MIO Control for Pin 5
MIO_PIN_06	0XF8000718	32	RW	0x000000	MIO Control for Pin 6
MIO_PIN_07	0XF800071C	32	RW	0x000000	MIO Control for Pin 7
MIO_PIN_08	0XF8000720	32	RW	0x000000	MIO Control for Pin 8
MIO_PIN_09	0XF8000724	32	RW	0x000000	MIO Control for Pin 9
MIO_PIN_10	0XF8000728	32	RW	0x000000	MIO Control for Pin 10
MIO_PIN_11	0XF800072C	32	RW	0x000000	MIO Control for Pin 11
MIO_PIN_12	0XF8000730	32	RW	0x000000	MIO Control for Pin 12
MIO_PIN_13	0XF8000734	32	RW	0x000000	MIO Control for Pin 13
MIO_PIN_14	0XF8000738	32	RW	0x000000	MIO Control for Pin 14
MIO_PIN_15	0XF800073C	32	RW	0x000000	MIO Control for Pin 15
MIO_PIN_28	0XF8000770	32	RW	0x000000	MIO Control for Pin 28
MIO_PIN_29	0XF8000774	32	RW	0x000000	MIO Control for Pin 29
MIO_PIN_30	0XF8000778	32	RW	0x000000	MIO Control for Pin 30
MIO_PIN_31	0XF800077C	32	RW	0x000000	MIO Control for Pin 31
MIO_PIN_32	0XF8000780	32	RW	0x000000	MIO Control for Pin 32
MIO_PIN_33	0XF8000784	32	RW	0x000000	MIO Control for Pin 33
MIO_PIN_34	0XF8000788	32	RW	0x000000	MIO Control for Pin 34
MIO_PIN_35	0XF800078C	32	RW	0x000000	MIO Control for Pin 35
MIO_PIN_36	0XF8000790	32	RW	0x000000	MIO Control for Pin 36
MIO_PIN_37	0XF8000794	32	RW	0x000000	MIO Control for Pin 37
MIO_PIN_38	0XF8000798	32	RW	0x000000	MIO Control for Pin 38
MIO_PIN_39	0XF800079C	32	RW	0x000000	MIO Control for Pin 39
MIO_PIN_48	0XF80007C0	32	RW	0x000000	MIO Control for Pin 48
MIO_PIN_49	0XF80007C4	32	RW	0x000000	MIO Control for Pin 49
MIO_PIN_52	0XF80007D0	32	RW	0x000000	MIO Control for Pin 52
MIO_PIN_53	0XF80007D4	32	RW	0x000000	MIO Control for Pin 53
SLCR_LOCK	0XF8000004	32	WO	0x000000	SLCR Write Protection Lock

ps7_mio_init_data_1_0

SLCR SETTINGS

Register ( slcr )SLCR_UNLOCK

Register Name

Address

Width

Type

Reset Value

Description

Register Name	Address	Width	Type	Reset Value	Description
SLCR_UNLOCK	0XF8000008	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
UNLOCK_KEY	15:0	ffff	df0d	df0d	When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero.
SLCR_UNLOCK@0XF8000008	31:0	ffff		df0d	SLCR Write Protection Unlock

OCM REMAPPING

MIO PROGRAMMING

Register ( slcr )MIO_PIN_00

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_00	0XF8000700	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Tri-state enable, active high.
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out_upper- (QSPI Upper select)
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
L2_SEL	4:3	18	0	0	Level 2 Mux Select 0= Level 3 Mux Output 1= smc_cs0, Output, smc_sram_cs_n[0]- (SRAM CS0) 2= nand_cs, Output, smc_nand_cs_n- (NAND chip select) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used
Speed	8:8	100	0	0	Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
IO_Type	11:9	e00	3	600	Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
PULLUP	12:12	1000	1	1000	Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
DisableRcvr	13:13	2000	0	0	Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
MIO_PIN_00@0XF8000700	31:0	3fff		1600	MIO Control for Pin 0

Register ( slcr )MIO_PIN_01

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_01	0XF8000704	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Tri-state enable, active high.
L0_SEL	1:1	2	1	2	Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out- (QSPI Select)
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
L2_SEL	4:3	18	0	0	Level 2 Mux Select 0= Level 3 Mux Output 1= smc_a25, Output, smc_sram_add[25]- (SRAM Address) 2= smc_cs1, Output, smc_sram_cs_n[1]- (SRAM CS1) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used
Speed	8:8	100	0	0	Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
IO_Type	11:9	e00	3	600	Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
PULLUP	12:12	1000	1	1000	Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
DisableRcvr	13:13	2000	0	0	Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
MIO_PIN_01@0XF8000704	31:0	3fff		1602	MIO Control for Pin 1

Register ( slcr )MIO_PIN_02

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_02	0XF8000708	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Tri-state enable, active high.
L0_SEL	1:1	2	1	2	Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus)
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[8]- (Trace Port Databus)
L2_SEL	4:3	18	0	0	Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_clk- (SRAM Clock) 2= nand, Output, smc_nand_ale- (NAND Address Latch Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used
Speed	8:8	100	0	0	Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
IO_Type	11:9	e00	3	600	Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
PULLUP	12:12	1000	0	0	Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[0]
DisableRcvr	13:13	2000	0	0	Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
MIO_PIN_02@0XF8000708	31:0	3fff		602	MIO Control for Pin 2

Register ( slcr )MIO_PIN_03

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_03	0XF800070C	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Tri-state enable, active high.
L0_SEL	1:1	2	1	2	Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus)
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[9]- (Trace Port Databus)
L2_SEL	4:3	18	0	0	Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[0]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[0]- (SRAM Data) 2= nand, Output, smc_nand_we_b- (NAND Write Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used
Speed	8:8	100	0	0	Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
IO_Type	11:9	e00	3	600	Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
PULLUP	12:12	1000	0	0	Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[1]
DisableRcvr	13:13	2000	0	0	Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
MIO_PIN_03@0XF800070C	31:0	3fff		602	MIO Control for Pin 3

Register ( slcr )MIO_PIN_04

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_04	0XF8000710	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Tri-state enable, active high.
L0_SEL	1:1	2	1	2	Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus)
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[10]- (Trace Port Databus)
L2_SEL	4:3	18	0	0	Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[1]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[1]- (SRAM Data) 2= nand, Input, smc_nand_data_in[2]- (NAND Data Bus) = nand, Output, smc_nand_data_out[2]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used
Speed	8:8	100	0	0	Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
IO_Type	11:9	e00	3	600	Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
PULLUP	12:12	1000	0	0	Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[2]
DisableRcvr	13:13	2000	0	0	Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
MIO_PIN_04@0XF8000710	31:0	3fff		602	MIO Control for Pin 4

Register ( slcr )MIO_PIN_05

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_05	0XF8000714	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Tri-state enable, active high.
L0_SEL	1:1	2	1	2	Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus)
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[11]- (Trace Port Databus)
L2_SEL	4:3	18	0	0	Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[2]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[2]- (SRAM Data) 2= nand, Input, smc_nand_data_in[0]- (NAND Data Bus) = nand, Output, smc_nand_data_out[0]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used
Speed	8:8	100	0	0	Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
IO_Type	11:9	e00	3	600	Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
PULLUP	12:12	1000	0	0	Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[3]
DisableRcvr	13:13	2000	0	0	Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
MIO_PIN_05@0XF8000714	31:0	3fff		602	MIO Control for Pin 5

Register ( slcr )MIO_PIN_06

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_06	0XF8000718	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Tri-state enable, active high.
L0_SEL	1:1	2	1	2	Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock)
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[12]- (Trace Port Databus)
L2_SEL	4:3	18	0	0	Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[3]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[3]- (SRAM Data) 2= nand, Input, smc_nand_data_in[1]- (NAND Data Bus) = nand, Output, smc_nand_data_out[1]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used
Speed	8:8	100	0	0	Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
IO_Type	11:9	e00	3	600	Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
PULLUP	12:12	1000	0	0	Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[4]
DisableRcvr	13:13	2000	0	0	Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
MIO_PIN_06@0XF8000718	31:0	3fff		602	MIO Control for Pin 6

Register ( slcr )MIO_PIN_07

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_07	0XF800071C	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Tri-state enable, active high.
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[13]- (Trace Port Databus)
L2_SEL	4:3	18	0	0	Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_oe_b- (SRAM Output enable) 2= nand, Output, smc_nand_cle- (NAND Command Latch Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used
Speed	8:8	100	0	0	Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
IO_Type	11:9	e00	3	600	Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
PULLUP	12:12	1000	0	0	Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[0]
DisableRcvr	13:13	2000	0	0	Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
MIO_PIN_07@0XF800071C	31:0	3fff		600	MIO Control for Pin 7

Register ( slcr )MIO_PIN_08

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_08	0XF8000720	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Tri-state enable, active high.
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back)
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[14]- (Trace Port Databus)
L2_SEL	4:3	18	0	0	Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_we_b- (SRAM Write enable) 2= nand, Output, smc_nand_re_b- (NAND Read Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)
Speed	8:8	100	0	0	Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
IO_Type	11:9	e00	3	600	Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
PULLUP	12:12	1000	0	0	Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[1]
DisableRcvr	13:13	2000	0	0	Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
MIO_PIN_08@0XF8000720	31:0	3fff		600	MIO Control for Pin 8

Register ( slcr )MIO_PIN_09

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_09	0XF8000724	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Tri-state enable, active high.
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock)
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[15]- (Trace Port Databus)
L2_SEL	4:3	18	0	0	Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[6]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[6]- (SRAM Data) 2= nand, Input, smc_nand_data_in[4]- (NAND Data Bus) = nand, Output, smc_nand_data_out[4]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)
Speed	8:8	100	0	0	Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
IO_Type	11:9	e00	3	600	Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
PULLUP	12:12	1000	1	1000	Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
DisableRcvr	13:13	2000	0	0	Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
MIO_PIN_09@0XF8000724	31:0	3fff		1600	MIO Control for Pin 9

Register ( slcr )MIO_PIN_10

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_10	0XF8000728	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Tri-state enable, active high.
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper Databus)
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus)
L2_SEL	4:3	18	0	0	Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[7]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[7]- (SRAM Data) 2= nand, Input, smc_nand_data_in[5]- (NAND Data Bus) = nand, Output, smc_nand_data_out[5]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)
Speed	8:8	100	0	0	Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
IO_Type	11:9	e00	3	600	Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
PULLUP	12:12	1000	1	1000	Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
DisableRcvr	13:13	2000	0	0	Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
MIO_PIN_10@0XF8000728	31:0	3fff		1600	MIO Control for Pin 10

Register ( slcr )MIO_PIN_11

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_11	0XF800072C	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Tri-state enable, active high.
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper Databus)
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus)
L2_SEL	4:3	18	0	0	Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[4]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[4]- (SRAM Data) 2= nand, Input, smc_nand_data_in[6]- (NAND Data Bus) = nand, Output, smc_nand_data_out[6]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)
Speed	8:8	100	0	0	Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
IO_Type	11:9	e00	3	600	Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
PULLUP	12:12	1000	1	1000	Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
DisableRcvr	13:13	2000	0	0	Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
MIO_PIN_11@0XF800072C	31:0	3fff		1600	MIO Control for Pin 11

Register ( slcr )MIO_PIN_12

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_12	0XF8000730	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Tri-state enable, active high.
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper Databus)
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock)
L2_SEL	4:3	18	0	0	Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_wait- (SRAM Wait State indicator) 2= nand, Input, smc_nand_data_in[7]- (NAND Data Bus) = nand, Output, smc_nand_data_out[7]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)
Speed	8:8	100	0	0	Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
IO_Type	11:9	e00	3	600	Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
PULLUP	12:12	1000	1	1000	Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
DisableRcvr	13:13	2000	0	0	Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
MIO_PIN_12@0XF8000730	31:0	3fff		1600	MIO Control for Pin 12

Register ( slcr )MIO_PIN_13

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_13	0XF8000734	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Tri-state enable, active high.
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper Databus)
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal)
L2_SEL	4:3	18	0	0	Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[5]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[5]- (SRAM Data) 2= nand, Input, smc_nand_data_in[3]- (NAND Data Bus) = nand, Output, smc_nand_data_out[3]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)
Speed	8:8	100	0	0	Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
IO_Type	11:9	e00	3	600	Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
PULLUP	12:12	1000	1	1000	Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
DisableRcvr	13:13	2000	0	0	Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
MIO_PIN_13@0XF8000734	31:0	3fff		1600	MIO Control for Pin 13

Register ( slcr )MIO_PIN_14

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_14	0XF8000738	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Tri-state enable, active high.
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus)
L2_SEL	4:3	18	0	0	Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_fbclk- (SRAM Feedback Clock) 2= nand, Input, smc_nand_busy- (NAND Busy) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)
Speed	8:8	100	0	0	Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
IO_Type	11:9	e00	3	600	Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
PULLUP	12:12	1000	1	1000	Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
DisableRcvr	13:13	2000	0	0	Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
MIO_PIN_14@0XF8000738	31:0	3fff		1600	MIO Control for Pin 14

Register ( slcr )MIO_PIN_15

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_15	0XF800073C	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Tri-state enable, active high.
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus)
L2_SEL	4:3	18	0	0	Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[0]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)
Speed	8:8	100	0	0	Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
IO_Type	11:9	e00	3	600	Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
PULLUP	12:12	1000	1	1000	Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
DisableRcvr	13:13	2000	0	0	Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
MIO_PIN_15@0XF800073C	31:0	3fff		1600	MIO Control for Pin 15

Register ( slcr )MIO_PIN_28

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_28	0XF8000770	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Tri-state enable, active high.
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock)
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data bus)
L2_SEL	4:3	18	0	0	Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[13]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[28]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[28]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output)
Speed	8:8	100	0	0	Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
IO_Type	11:9	e00	3	600	Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
PULLUP	12:12	1000	1	1000	Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
DisableRcvr	13:13	2000	0	0	Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
MIO_PIN_28@0XF8000770	31:0	3fff		1600	MIO Control for Pin 28

Register ( slcr )MIO_PIN_29

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_29	0XF8000774	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Tri-state enable, active high.
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data)
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control)
L2_SEL	4:3	18	0	0	Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[14]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[29]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[29]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input)
Speed	8:8	100	0	0	Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
IO_Type	11:9	e00	3	600	Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
PULLUP	12:12	1000	1	1000	Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
DisableRcvr	13:13	2000	0	0	Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
MIO_PIN_29@0XF8000774	31:0	3fff		1600	MIO Control for Pin 29

Register ( slcr )MIO_PIN_30

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_30	0XF8000778	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Tri-state enable, active high.
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data)
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers)
L2_SEL	4:3	18	0	0	Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[15]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[30]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[30]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input)
Speed	8:8	100	0	0	Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
IO_Type	11:9	e00	3	600	Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
PULLUP	12:12	1000	1	1000	Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
DisableRcvr	13:13	2000	0	0	Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
MIO_PIN_30@0XF8000778	31:0	3fff		1600	MIO Control for Pin 30

Register ( slcr )MIO_PIN_31

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_31	0XF800077C	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Tri-state enable, active high.
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data)
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY)
L2_SEL	4:3	18	0	0	Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[16]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[31]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[31]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output)
Speed	8:8	100	0	0	Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
IO_Type	11:9	e00	3	600	Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
PULLUP	12:12	1000	1	1000	Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
DisableRcvr	13:13	2000	0	0	Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
MIO_PIN_31@0XF800077C	31:0	3fff		1600	MIO Control for Pin 31

Register ( slcr )MIO_PIN_32

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_32	0XF8000780	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Tri-state enable, active high.
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data)
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data bus)
L2_SEL	4:3	18	0	0	Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[17]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)
Speed	8:8	100	0	0	Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
IO_Type	11:9	e00	3	600	Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
PULLUP	12:12	1000	1	1000	Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
DisableRcvr	13:13	2000	0	0	Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
MIO_PIN_32@0XF8000780	31:0	3fff		1600	MIO Control for Pin 32

Register ( slcr )MIO_PIN_33

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_33	0XF8000784	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Tri-state enable, active high.
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control)
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data bus)
L2_SEL	4:3	18	0	0	Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[18]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)
Speed	8:8	100	0	0	Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
IO_Type	11:9	e00	3	600	Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
PULLUP	12:12	1000	1	1000	Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
DisableRcvr	13:13	2000	0	0	Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
MIO_PIN_33@0XF8000784	31:0	3fff		1600	MIO Control for Pin 33

Register ( slcr )MIO_PIN_34

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_34	0XF8000788	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Tri-state enable, active high.
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock)
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data bus)
L2_SEL	4:3	18	0	0	Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[19]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)
Speed	8:8	100	0	0	Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
IO_Type	11:9	e00	3	600	Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
PULLUP	12:12	1000	1	1000	Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
DisableRcvr	13:13	2000	0	0	Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
MIO_PIN_34@0XF8000788	31:0	3fff		1600	MIO Control for Pin 34

Register ( slcr )MIO_PIN_35

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_35	0XF800078C	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Tri-state enable, active high.
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data)
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data bus)
L2_SEL	4:3	18	0	0	Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[20]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)
Speed	8:8	100	0	0	Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
IO_Type	11:9	e00	3	600	Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
PULLUP	12:12	1000	1	1000	Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
DisableRcvr	13:13	2000	0	0	Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
MIO_PIN_35@0XF800078C	31:0	3fff		1600	MIO Control for Pin 35

Register ( slcr )MIO_PIN_36

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_36	0XF8000790	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Tri-state enable, active high.
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data)
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_xcvr_clk_in- (ULPI clock) 1= usb0, Output, usb0_xcvr_clk_out- (ULPI clock)
L2_SEL	4:3	18	0	0	Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[21]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)
Speed	8:8	100	0	0	Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
IO_Type	11:9	e00	3	600	Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
PULLUP	12:12	1000	1	1000	Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
DisableRcvr	13:13	2000	0	0	Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
MIO_PIN_36@0XF8000790	31:0	3fff		1600	MIO Control for Pin 36

Register ( slcr )MIO_PIN_37

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_37	0XF8000794	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Tri-state enable, active high.
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data)
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data bus)
L2_SEL	4:3	18	0	0	Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[22]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)
Speed	8:8	100	0	0	Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
IO_Type	11:9	e00	3	600	Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
PULLUP	12:12	1000	1	1000	Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
DisableRcvr	13:13	2000	0	0	Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
MIO_PIN_37@0XF8000794	31:0	3fff		1600	MIO Control for Pin 37

Register ( slcr )MIO_PIN_38

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_38	0XF8000798	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Tri-state enable, active high.
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data)
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data bus)
L2_SEL	4:3	18	0	0	Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[23]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)
Speed	8:8	100	0	0	Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
IO_Type	11:9	e00	3	600	Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
PULLUP	12:12	1000	1	1000	Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
DisableRcvr	13:13	2000	0	0	Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
MIO_PIN_38@0XF8000798	31:0	3fff		1600	MIO Control for Pin 38

Register ( slcr )MIO_PIN_39

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_39	0XF800079C	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Tri-state enable, active high.
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control )
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data bus)
L2_SEL	4:3	18	0	0	Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[24]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)
Speed	8:8	100	0	0	Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
IO_Type	11:9	e00	3	600	Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
PULLUP	12:12	1000	1	1000	Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
DisableRcvr	13:13	2000	0	0	Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
MIO_PIN_39@0XF800079C	31:0	3fff		1600	MIO Control for Pin 39

Register ( slcr )MIO_PIN_48

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_48	0XF80007C0	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Tri-state enable, active high.
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_xcvr_clk_in- (ULPI Clock) 1= usb1, Output, usb1_xcvr_clk_out- (ULPI Clock)
L2_SEL	4:3	18	0	0	Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)
Speed	8:8	100	0	0	Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
IO_Type	11:9	e00	3	600	Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
PULLUP	12:12	1000	1	1000	Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
DisableRcvr	13:13	2000	0	0	Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
MIO_PIN_48@0XF80007C0	31:0	3fff		1600	MIO Control for Pin 48

Register ( slcr )MIO_PIN_49

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_49	0XF80007C4	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Tri-state enable, active high.
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data bus)
L2_SEL	4:3	18	0	0	Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)
Speed	8:8	100	0	0	Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
IO_Type	11:9	e00	3	600	Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
PULLUP	12:12	1000	1	1000	Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
DisableRcvr	13:13	2000	0	0	Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
MIO_PIN_49@0XF80007C4	31:0	3fff		1600	MIO Control for Pin 49

Register ( slcr )MIO_PIN_52

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_52	0XF80007D0	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Tri-state enable, active high.
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
L2_SEL	4:3	18	0	0	Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= mdio0, Output, gem0_mdc- (MDIO Clock) 5= mdio1, Output, gem1_mdc- (MDIO Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)
Speed	8:8	100	0	0	Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
IO_Type	11:9	e00	3	600	Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
PULLUP	12:12	1000	1	1000	Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
DisableRcvr	13:13	2000	0	0	Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
MIO_PIN_52@0XF80007D0	31:0	3fff		1600	MIO Control for Pin 52

Register ( slcr )MIO_PIN_53

Register Name	Address	Width	Type	Reset Value	Description
MIO_PIN_53	0XF80007D4	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
TRI_ENABLE	0:0	1	0	0	Tri-state enable, active high.
L0_SEL	1:1	2	0	0	Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
L1_SEL	2:2	4	0	0	Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
L2_SEL	4:3	18	0	0	Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
L3_SEL	7:5	e0	0	0	Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= mdio0, Input, gem0_mdio_in- (MDIO Data) 4= mdio0, Output, gem0_mdio_out- (MDIO Data) 5= mdio1, Input, gem1_mdio_in- (MDIO Data) 5= mdio1, Output, gem1_mdio_out- (MDIO Data) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)
Speed	8:8	100	0	0	Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
IO_Type	11:9	e00	3	600	Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
PULLUP	12:12	1000	1	1000	Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
DisableRcvr	13:13	2000	0	0	Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
MIO_PIN_53@0XF80007D4	31:0	3fff		1600	MIO Control for Pin 53

LOCK IT BACK

Register ( slcr )SLCR_LOCK

Register Name	Address	Width	Type	Reset Value	Description
SLCR_LOCK	0XF8000004	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
LOCK_KEY	15:0	ffff	767b	767b	When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero.
SLCR_LOCK@0XF8000004	31:0	ffff		767b	SLCR Write Protection Lock

ps7_peripherals_init_data_1_0

Register Name	Address	Width	Type	Reset Value	Description
SLCR_UNLOCK	0XF8000008	32	WO	0x000000	SLCR Write Protection Unlock
SLCR_LOCK	0XF8000004	32	WO	0x000000	SLCR Write Protection Lock
Baud_rate_divider_reg0	0XE0000034	32	RW	0x000000	baud rate divider register
Baud_rate_gen_reg0	0XE0000018	32	RW	0x000000	Baud rate divider register
Control_reg0	0XE0000000	32	RW	0x000000	UART Control register
mode_reg0	0XE0000004	32	RW	0x000000	UART Mode register
Config_reg	0XE000D000	32	RW	0x000000	SPI configuration register
CTRL	0XF8007000	32	RW	0x000000	Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.

ps7_peripherals_init_data_1_0

SLCR SETTINGS

Register ( slcr )SLCR_UNLOCK

Register Name

Address

Width

Type

Reset Value

Description

Register Name	Address	Width	Type	Reset Value	Description
SLCR_UNLOCK	0XF8000008	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
UNLOCK_KEY	15:0	ffff	df0d	df0d	When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero.
SLCR_UNLOCK@0XF8000008	31:0	ffff		df0d	SLCR Write Protection Unlock

LOCK IT BACK

Register ( slcr )SLCR_LOCK

Register Name	Address	Width	Type	Reset Value	Description
SLCR_LOCK	0XF8000004	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
LOCK_KEY	15:0	ffff	767b	767b	When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero.
SLCR_LOCK@0XF8000004	31:0	ffff		767b	SLCR Write Protection Lock

SRAM/NOR SET OPMODE

UART REGISTERS

Register ( slcr )Baud_rate_divider_reg0

Register Name	Address	Width	Type	Reset Value	Description
Baud_rate_divider_reg0	0XE0000034	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
BDIV	7:0	ff	6	6	Baud rate divider value 0 - 3: ignored 4 - 255: Baud rate
Baud_rate_divider_reg0@0XE0000034	31:0	ff		6	baud rate divider register

Register ( slcr )Baud_rate_gen_reg0

Register Name	Address	Width	Type	Reset Value	Description
Baud_rate_gen_reg0	0XE0000018	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
CD	15:0	ffff	7c	7c	Baud Rate Clock Divisor Value 0 = Disables baud_sample 1 = Clock divisor bypass 2 - 65535 = baud_sample value
Baud_rate_gen_reg0@0XE0000018	31:0	ffff		7c	Baud rate divider register

Register ( slcr )Control_reg0

Register Name	Address	Width	Type	Reset Value	Description
Control_reg0	0XE0000000	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
STPBRK	8:8	100	0	0	Stop transmitter break. 1 = stop transmission of the break.
STTBRK	7:7	80	0	0	Start transmitter break 1 = start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high.
RSTTO	6:6	40	0	0	Restart receiver timeout counter 1 = receiver timeout counter is restarted
TXDIS	5:5	20	0	0	Transmit disable. 1, the transmitter is disabled
TXEN	4:4	10	1	10	Transmit enable. 1, the transmitter is enabled, provided the TXDIS field is set to 0.
RXDIS	3:3	8	0	0	Receive disable. 1= receiver is enabled
RXEN	2:2	4	1	4	Receive enable. 1=the receiver logic is enabled, provided RXDIS field is set to 0
TXRES	1:1	2	1	2	Software reset for TX data path. 1=the transmitter logic is reset and all pending transmitter data is discarded self clear
RXRES	0:0	1	1	1	Software reset for RX data path 1=receiver logic is reset and all pending receiver data is discarded self clear
Control_reg0@0XE0000000	31:0	1ff		17	UART Control register

Register ( slcr )mode_reg0

Register Name	Address	Width	Type	Reset Value	Description
mode_reg0	0XE0000004	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
IRMODE	11:11	800	0	0	Enable IrDA mode 0 : Default UART mode 1 : Enable IrDA mode
UCLKEN	10:10	400	0	0	External uart_clk source select 0 : APB clock, pclk 1 : a user-defined clock
CHMODE	9:8	300	0	0	Channel mode 00 = normal 01 = automatic cho 10 = local loopback 11 = remote loopback
NBSTOP	7:6	c0	0	0	Number of stop bits 00 = 1 stop bit 01 = 1.5 stop bits 10 = 2 stop bits 11 = reserved
PAR	5:3	38	4	20	Parity type select. 000 = even parity 001 = odd parity 010 = forced to 0 parity (space) 011 = forced to 1 parity (mark) 1xx = no parity
CHRL	2:1	6	0	0	Character length select 11 = 6 bits 10 = 7 bits 01 / 00 = 8 bits
CLKS	0:0	1	0	0	clock source select 1 = clock source is uart_clk/8 0 = clock source is uart_clk
mode_reg0@0XE0000004	31:0	fff		20	UART Mode register

QSPI REGISTERS

Register ( slcr )Config_reg

Register Name	Address	Width	Type	Reset Value	Description
Config_reg	0XE000D000	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
Holdb_dr	19:19	80000	1	80000	Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode.
Config_reg@0XE000D000	31:0	80000		80000	SPI configuration register

PL POWER ON RESET REGISTERS

Register ( slcr )CTRL

Register Name	Address	Width	Type	Reset Value	Description
CTRL	0XF8007000	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
PCFG_POR_CNT_4K	29:29	20000000	0	0	This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer
CTRL@0XF8007000	31:0	20000000		0	Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.

SMC TIMING CALCULATION REGISTER UPDATE

NAND SET CYCLE

OPMODE

DIRECT COMMAND

SRAM/NOR CS0 SET CYCLE

DIRECT COMMAND

NOR CS0 BASE ADDRESS

SRAM/NOR CS1 SET CYCLE

DIRECT COMMAND

NOR CS1 BASE ADDRESS

USB RESET

ENET RESET

I2C RESET

NOR CHIP SELECT

DIR MODE BANK 0

MASK_DATA_0_LSW HIGH BANK [15:0]

OUTPUT ENABLE BANK 0

ps7_post_config_1_0

Register Name	Address	Width	Type	Reset Value	Description
SLCR_UNLOCK	0XF8000008	32	WO	0x000000	SLCR Write Protection Unlock
LVL_SHFTR_EN	0XF8000900	32	RW	0x000000	Level Shifters Enable
FPGA_RST_CTRL	0XF8000240	32	RW	0x000000	FPGA Software Reset Control
SLCR_LOCK	0XF8000004	32	WO	0x000000	SLCR Write Protection Lock

ps7_post_config_1_0

SLCR SETTINGS

Register ( slcr )SLCR_UNLOCK

Register Name

Address

Width

Type

Reset Value

Description

Register Name	Address	Width	Type	Reset Value	Description
SLCR_UNLOCK	0XF8000008	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
UNLOCK_KEY	15:0	ffff	df0d	df0d	When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero.
SLCR_UNLOCK@0XF8000008	31:0	ffff		df0d	SLCR Write Protection Unlock

ENABLING LEVEL SHIFTER

Register ( slcr )LVL_SHFTR_EN

Register Name	Address	Width	Type	Reset Value	Description
LVL_SHFTR_EN	0XF8000900	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
USER_INP_ICT_EN_0	1:0	3	3	3	Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0].
USER_INP_ICT_EN_1	3:2	c	3	c	Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0].
LVL_SHFTR_EN@0XF8000900	31:0	f		f	Level Shifters Enable

FPGA RESETS TO 0

Register ( slcr )FPGA_RST_CTRL

Register Name	Address	Width	Type	Reset Value	Description
FPGA_RST_CTRL	0XF8000240	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
reserved_3	31:25	fe000000	0	0	Reserved. Writes are ignored, read data is always zero.
FPGA_ACP_RST	24:24	1000000	0	0	FPGA ACP port soft reset. 0 - No reset. 1 - ACP AXI interface reset output asserted.
FPGA_AXDS3_RST	23:23	800000	0	0	AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS3AXI interface reset output asserted.
FPGA_AXDS2_RST	22:22	400000	0	0	AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS2 AXI interface reset output asserted.
FPGA_AXDS1_RST	21:21	200000	0	0	AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS1 AXI interface reset output asserted.
FPGA_AXDS0_RST	20:20	100000	0	0	AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS0 AXI interface reset output asserted.
reserved_2	19:18	c0000	0	0	Reserved. Writes are ignored, read data is always zero.
FSSW1_FPGA_RST	17:17	20000	0	0	General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 1 reset is asserted.
FSSW0_FPGA_RST	16:16	10000	0	0	General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 0 reset is asserted.
reserved_1	15:14	c000	0	0	Reserved. Writes are ignored, read data is always zero.
FPGA_FMSW1_RST	13:13	2000	0	0	General purpose FPGA master interface 1 soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0 - No reset. 1 - FPGA master interface 1 reset is asserted.
FPGA_FMSW0_RST	12:12	1000	0	0	General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0 - No reset. 1 - FPGA master interface 0 reset is asserted.
FPGA_DMA3_RST	11:11	800	0	0	FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 3 peripheral request reset output asserted.
FPGA_DMA2_RST	10:10	400	0	0	FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 2 peripheral request reset output asserted.
FPGA_DMA1_RST	9:9	200	0	0	FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 1 peripheral request reset output asserted.
FPGA_DMA0_RST	8:8	100	0	0	FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 0 peripheral request reset output asserted.
reserved	7:4	f0	0	0	Reserved. Writes are ignored, read data is always zero.
FPGA3_OUT_RST	3:3	8	0	0	FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0 - No reset. 1 - FPGA 3 top level reset output asserted.
FPGA2_OUT_RST	2:2	4	0	0	FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0 - No reset. 1 - FPGA 2 top level reset output asserted.
FPGA1_OUT_RST	1:1	2	0	0	FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0 - No reset. 1 - FPGA 1 top level reset output asserted.
FPGA0_OUT_RST	0:0	1	0	0	FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0 - No reset. 1 - FPGA 0 top level reset output asserted.
FPGA_RST_CTRL@0XF8000240	31:0	ffffffff		0	FPGA Software Reset Control

AFI REGISTERS

AFI0 REGISTERS

AFI1 REGISTERS

AFI2 REGISTERS

AFI3 REGISTERS

LOCK IT BACK

Register ( slcr )SLCR_LOCK

Register Name	Address	Width	Type	Reset Value	Description
SLCR_LOCK	0XF8000004	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
LOCK_KEY	15:0	ffff	767b	767b	When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero.
SLCR_LOCK@0XF8000004	31:0	ffff		767b	SLCR Write Protection Lock

ps7_debug_1_0

Register Name	Address	Width	Type	Reset Value	Description
LAR	0XF8898FB0	32	WO	0x000000	Lock Access Register
LAR	0XF8899FB0	32	WO	0x000000	Lock Access Register
LAR	0XF8809FB0	32	WO	0x000000	Lock Access Register

ps7_debug_1_0

CROSS TRIGGER CONFIGURATIONS

UNLOCKING CTI REGISTERS

Register ( slcr )LAR

Register Name

Address

Width

Type

Reset Value

Description

Register Name	Address	Width	Type	Reset Value	Description
LAR	0XF8898FB0	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
KEY	31:0	ffffffff	c5acce55	c5acce55	Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.
LAR@0XF8898FB0	31:0	ffffffff		c5acce55	Lock Access Register

Register ( slcr )LAR

Register Name	Address	Width	Type	Reset Value	Description
LAR	0XF8899FB0	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
KEY	31:0	ffffffff	c5acce55	c5acce55	Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.
LAR@0XF8899FB0	31:0	ffffffff		c5acce55	Lock Access Register

Register ( slcr )LAR

Register Name	Address	Width	Type	Reset Value	Description
LAR	0XF8809FB0	32	rw	0x00000000	--

Field Name	Bits	Mask	Value	Shifted Value	Description
KEY	31:0	ffffffff	c5acce55	c5acce55	Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.
LAR@0XF8809FB0	31:0	ffffffff		c5acce55	Lock Access Register

ENABLING CTI MODULES AND CHANNELS

MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS