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1
UltraScale / Re: TE0820 Power consumption reduction
« Last post by JH on Today at 08:09:04 AM »
Hi,
which Vivado/Vitis version did you use?
I've test it one time on my place and it works.
I've use our 2020.2 design:
https://wiki.trenz-electronic.de/display/PD/TE0820+Test+Board
1. create the project with the selection guide and 2020.2
2. open Block Design and select the ZynqMP IP --> go to memory and change effective dram bus width to 16
3. Generate bitstream -> use console and type TE::hw_build_design -export_prebuilt
4. Start Vitis generation with our scripts: TE::sw_run_vitis -all
use the new generated Hello TE0820 boot.bin from your assembly variant and boot from SD(is faster, QSPI should also work)

br
John
2
UltraScale / Re: TE0820 Power consumption reduction
« Last post by engkan2kit on September 27, 2021, 05:32:07 PM »
Thanks John.

I used to use Vitis in generating the FSBL but build, compiling it is so slow and it's difficult to automate and change if we want to support different hardware.

I tried to build FSBL from Vitis just now and they have the same problem with the one I built with petalinux. It seems that I may have some other issues. I'll try to run the DRAM and MEM test applications. However I have not done this before with TE0820. Since I can't set TE0820 to JTAG mode (only SD and QSPI), do I need to flash memory test application to QSPI first?

Thanks.
3
UltraScale / Re: TE0820 Power consumption reduction
« Last post by JH on September 27, 2021, 08:44:13 AM »
Hi,
Quote
I'm just patching the fsbl from petalinux.
I would not recommend this. I've heard from other customer, that FSBL from petalinux works different to FSBL from Vitis, when you add our changes as patch. Source code is the same, but maybe petalinux use other drivers or different compiler order or....


Quote
I'll try to setup a Vitis Workspace to do a memory test over the debug console. I had a Vitis workspace before but the flow takes to long just to generate the FSBL so I had to move it to petalinux.
I've some basic notes here:
https://wiki.trenz-electronic.de/display/PD/Vitis
It still not finish and Xilinx gas changed again style a little bit since I've start this documentation for Vitis, but it should help to find basic steps.

br
John
4
UltraScale / Re: TE0820 Power consumption reduction
« Last post by engkan2kit on September 27, 2021, 08:14:53 AM »
Hi,

I'm just patching the fsbl from petalinux. So taking the TE mods apply it to the embeddedsw repo, generate a patch, then, add an fsbl recipe to apply the patch in petalinux project. This is working fine and I can get the si5338 related configs correctly. After setting bus width to half, I compared the changes in the Zynqmp IP and only 3 changes are there after changing the effective bus width to 16. The first 1 is the offsets, the 2nd is the property of bus-width, and the 3rd one is the psu_protection__slaves property where the the range of low DDR range was changed as well.

I'll try to setup a Vitis Workspace to do a memory test over the debug console. I had a Vitis workspace before but the flow takes to long just to generate the FSBL so I had to move it to petalinux.

Thanks.
5
UltraScale / Re: TE0820 Power consumption reduction
« Last post by JH on September 27, 2021, 06:36:37 AM »
Hi,
did you use clean Vitis project or did you simple update(sometime xsa update will not recognise all changes)? You should try to generate completely new Vitis workspace.
What did you change? Only bus width? Or more?
Did you run memory test over Vitis debug console? Does it work?

 I think something else was going wrong as you has changed DDR setting.

br
John



 
6
UltraScale / Re: TE0820 Power consumption reduction
« Last post by engkan2kit on September 26, 2021, 07:28:42 PM »
Hi JH,

Thanks for your the ideas. I'm trying to reduce to 16bits the effective bandwidth of the DD4 and nothing else is changed. I also checked the TE modified FSBL source code to check if I need to change anything related to DDR4 but there was none so I rebuilt my codes and I'm now not able to boot. The booting got stuck in FSBL. This is what it looks like:
--------------------------------------------------------------------------------
QSPI 32 bit Boot Mode
FlashID=0x20 0xBB 0x20
XFSBL_ERROR_QSPI_LENGTH
Device Copy Failed
Boot Device Initialization failed 0x19
Fsbl Error Status: 0x00002019
Performing FSBL FallBack

FSBL tried to copy files from QSPI but it looks like QSPI is not working now. So I'm guessing that the DDR4 is causing this not working anymore because only the DDR4 property was changed. Is there something I need to do on the PMU FW and FSBL to make this work on the T0820-4EV/4CG or do I need to remove components in the board?

Thank you.
7
CYC1000 community projects / Re: Conecting external clock signal to the cyc1000
« Last post by sjoshi on September 24, 2021, 10:06:51 AM »
Thanks!
8
CYC1000 community projects / Re: Conecting external clock signal to the cyc1000
« Last post by Thomas D on September 24, 2021, 09:28:18 AM »
Hi,
I have marked the clk_x pad on the attached screenshot.

br
Thomas
10
CYC1000 community projects / Conecting external clock signal to the cyc1000
« Last post by sjoshi on September 19, 2021, 11:58:32 AM »
I am trying to connect an external board with a ULPI PHY to the CYC1000. I have to use the 60 MHz clock generated by this extrenal board to drive the logic within my CYC1000. I understand that if I use the rising_edge function on this signal then it has to be connected to a clock enabled input. From the schematics, I see that all such pins are grounded except two. One of those is the 12M onboard clock. The other is marked clk_x and is reserved for a crystal that is not connected.

Can I simply solder my clock signal to the free pad on the pcb? If yes,can someone point out which of the 4 pads is the output pad? I cannot figure it out somehow.
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