- Welcome to Trenz Electronic GmbH Support Forum.
Recent posts
#1
Trenz Electronic FPGA Modules / Re: QSPI Flash Issues on TE074...
Last post by alaney - September 19, 2024, 11:28:23 AMUPDATE:
I have built my design using 2024.1 "classic" and that BOOT.bin file works when programmed into QSPI flash. So, this is definitely something to do with the new Vitis tool. Just seems odd that a "new" Vitis created a BOOT.bin is ok on an SD card, but fails in QSPI flash.
I have built my design using 2024.1 "classic" and that BOOT.bin file works when programmed into QSPI flash. So, this is definitely something to do with the new Vitis tool. Just seems odd that a "new" Vitis created a BOOT.bin is ok on an SD card, but fails in QSPI flash.
#2
Trenz Electronic FPGA Modules / Re: QSPI Flash Issues on TE074...
Last post by alaney - September 18, 2024, 04:17:39 PMOur SoM has QR Code: 727724
I have tried the following so far:
1) SPI flashed your hello BOOT.bin file and that worked
2) Using Vitis "classic" 2024.1 instead of the new Vitis tool, I created a "peripheral test" example app still targeting my actual 2024.1 Vivado design. This also worked using QSPI.
3) I am now in the process of porting my SW across to Vitis "Classic" to see if that works.
Can you think of any reason why the new Vitis tool "may" have an issue, but only with QSPI flash? I guess there could be some setting in the FSBL that is built into the BOOT.bin that only causes an issue with QSPI? (I would quite like to get this working with the new Vitis tool if possible)
I have tried the following so far:
1) SPI flashed your hello BOOT.bin file and that worked
2) Using Vitis "classic" 2024.1 instead of the new Vitis tool, I created a "peripheral test" example app still targeting my actual 2024.1 Vivado design. This also worked using QSPI.
3) I am now in the process of porting my SW across to Vitis "Classic" to see if that works.
Can you think of any reason why the new Vitis tool "may" have an issue, but only with QSPI flash? I guess there could be some setting in the FSBL that is built into the BOOT.bin that only causes an issue with QSPI? (I would quite like to get this working with the new Vitis tool if possible)
#3
Trenz Electronic FPGA Modules / Re: TEI0022 DataStorm FPGA DDR...
Last post by MR - September 18, 2024, 12:14:10 AMThanks for the reply, but this design only has the HPS memory. I am looking for a design that utilizes the DDR3 attached to the non-HPS pins.
Thanks,
Matt
Thanks,
Matt
#4
EDDP-EDPS Support / Re: TE0950 Versal support on V...
Last post by M Kirberg - September 17, 2024, 10:18:27 AMHi,
you need the extensible platform flow.
Please write to trenz support email then I can provide you with a working TE0950 AI example code.
br
you need the extensible platform flow.
Please write to trenz support email then I can provide you with a working TE0950 AI example code.
br
#5
Trenz Electronic FPGA Modules / Re: QSPI Flash Issues on TE074...
Last post by JH - September 16, 2024, 09:05:52 AMHi,
your programming steps looks fine. You programmed QSPI with SD insert, so it was QSPI boot mode, but with older your SDK Version it's no matter, problems are only with newer one. When you change Boot Mode to JTAG only(without SD and DIP S1-1 OFF, than it should also be possible with newer Vivado/Vitis Version(but you need correct project with correct FSBL in this case too)).
Your Boot.bin should normally also be fine when it boots from SD.
At the moment I would expect it should works.
Do you see something on uart when you try to reboot with reset button from TE0790 programmer?
Can you tell me which assembly variant of the TE0745 you has or alternatively the serial number of the module(it's on the small sticker with QR Code)?
Can you try out one time our reference design boot.bin please?
https://wiki.trenz-electronic.de/display/PD/TE0745+Test+Board
-->direct Download link:https://shop.trenz-electronic.de/trenzdownloads/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/Reference_Design/2023.2/test_board/TE0745-test_board-vivado_2023.2-build_4_20240220094718.zip
Download includes also prebuilt binaries, use hello TE0745 example Boot.bin at first.
br
John
your programming steps looks fine. You programmed QSPI with SD insert, so it was QSPI boot mode, but with older your SDK Version it's no matter, problems are only with newer one. When you change Boot Mode to JTAG only(without SD and DIP S1-1 OFF, than it should also be possible with newer Vivado/Vitis Version(but you need correct project with correct FSBL in this case too)).
Your Boot.bin should normally also be fine when it boots from SD.
At the moment I would expect it should works.
Do you see something on uart when you try to reboot with reset button from TE0790 programmer?
Can you tell me which assembly variant of the TE0745 you has or alternatively the serial number of the module(it's on the small sticker with QR Code)?
Can you try out one time our reference design boot.bin please?
https://wiki.trenz-electronic.de/display/PD/TE0745+Test+Board
-->direct Download link:https://shop.trenz-electronic.de/trenzdownloads/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/Reference_Design/2023.2/test_board/TE0745-test_board-vivado_2023.2-build_4_20240220094718.zip
Download includes also prebuilt binaries, use hello TE0745 example Boot.bin at first.
br
John
#6
UltraScale / Re: TE0803 SOM - linux BSP
Last post by JH - September 16, 2024, 08:22:03 AMHi,
we have a reference design with petalinux(yocto based) template for TE0803 together with our TEBF0808 carrier. Documentation and downloads:
https://wiki.trenz-electronic.de/display/PD/TE0803+StarterKit
We didn't have buildroot examples, sorry.
br
John
we have a reference design with petalinux(yocto based) template for TE0803 together with our TEBF0808 carrier. Documentation and downloads:
https://wiki.trenz-electronic.de/display/PD/TE0803+StarterKit
We didn't have buildroot examples, sorry.
br
John
#7
UltraScale / TE0803 SOM - linux BSP
Last post by flatmax - September 15, 2024, 05:07:14 AMHi there,
Is there a Linux BSP for the TE0803 module ?
If not, what are people using to build Linux for the TE0803 module ?
Is there buildroot support ?
thanks
Matt
Is there a Linux BSP for the TE0803 module ?
If not, what are people using to build Linux for the TE0803 module ?
Is there buildroot support ?
thanks
Matt
#8
Trenz Electronic FPGA Modules / Re: Generating FSBL for TE0720...
Last post by JH - September 13, 2024, 01:14:39 PMHi,
TE0720-03-1CR and TE0720-04-61Q33MA use different DDR with different size.
Did you checked that your project use correct PS configuration?
You can import our FSBL with trenz modification as template into Vitis as local repository and use GUI:
https://wiki.trenz-electronic.de/display/PD/Vitis#Vitis-Includelocalrepositories
with newer Vivado/Vitis/Petalinux we offer also a patch for petalinux:
https://wiki.trenz-electronic.de/display/PD/TE0720+Test+Board
https://wiki.trenz-electronic.de/display/PD/TE0720+Test+Board#TE0720TestBoard-FSBLpatch(alternativeforvitisfsbltrenzpatch)
But this does work only with corresponding petalinux version.
But at the moment I would expect you use wrong PS configuration for memory.
PS Memmory setup is set to "MT41J64M16 JT-125G" on TE0720-03-1CR and "MT41J256M16 RE-125" on TE0720-04-61Q33MA. memory configuration will be done with fsbl and linux only need to know size, that's the reason why it works in the other way(or boot.bin and your linux files) and linux use less ddr.
br
John
TE0720-03-1CR and TE0720-04-61Q33MA use different DDR with different size.
Did you checked that your project use correct PS configuration?
You can import our FSBL with trenz modification as template into Vitis as local repository and use GUI:
https://wiki.trenz-electronic.de/display/PD/Vitis#Vitis-Includelocalrepositories
with newer Vivado/Vitis/Petalinux we offer also a patch for petalinux:
https://wiki.trenz-electronic.de/display/PD/TE0720+Test+Board
https://wiki.trenz-electronic.de/display/PD/TE0720+Test+Board#TE0720TestBoard-FSBLpatch(alternativeforvitisfsbltrenzpatch)
But this does work only with corresponding petalinux version.
But at the moment I would expect you use wrong PS configuration for memory.
PS Memmory setup is set to "MT41J64M16 JT-125G" on TE0720-03-1CR and "MT41J256M16 RE-125" on TE0720-04-61Q33MA. memory configuration will be done with fsbl and linux only need to know size, that's the reason why it works in the other way(or boot.bin and your linux files) and linux use less ddr.
br
John
#9
Trenz Electronic FPGA Modules / QSPI Flash Issues on TE0745
Last post by alaney - September 13, 2024, 01:10:22 PMI am trying to get my system to boot from QSPI flash, but am having issues. where this is what I have tried:
1) I have updated the CPLD to variant 2 allowing JTAG/QSPI/SD Card
2) My main project (bare metal) is using Vivado/Vitis 2024.1 where if I understand your wiki information the Vitis/SDK version has varying degrees of issues when programming the QSPI flash.
3) From this wiki I have installed 2017.2 (seemed the version with the least issues to me) and created an unrelated SDK fsbl application targeting a ZC702 board. I have only done this so that SDK then allows me to use the flash program application. I have then referenced the BOOT.bin file from my 2024.1 project in the flash programming tool and programed/verified successfully. Here is the console op during flashing:
cmd /C program_flash -f \
G:\Vitis_Workspace_2024\SW_Application\BOOT.bin \
-offset 0 -flash_type qspi_single -blank_check -verify -cable type xilinx_tcf url \
TCP:127.0.0.1:3121
****** Xilinx Program Flash
****** Program Flash v2017.2 (64-bit)
**** SW Build 1909853 on Thu Jun 15 18:39:09 MDT 2017
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
Connecting to hw_server @ TCP:127.0.0.1:3121
Connected to hw_server @ TCP:127.0.0.1:3121
Available targets and devices:
Target 0 : jsn-JTAG-ONB4-251633006C35A
Device 0: jsn-JTAG-ONB4-251633006C35A-4ba00477-0
Retrieving Flash info...
Initialization done, programming the memory
BOOT_MODE REG = 0x00000001
WARNING: [Xicom 50-100] The current boot mode is QSPI.
If flash programming fails, configure device for JTAG boot mode and try again.
f probe 0 0 0
Performing Erase Operation...
Erase Operation successful.
INFO: [Xicom 50-44] Elapsed time = 7 sec.
Performing Blank Check Operation...
0%...10%...20%...30%...40%...50%...60%...70%...80%...90%...100%
INFO: [Xicom 50-44] Elapsed time = 39 sec.
Blank Check Operation successful. The part is blank.
Performing Program Operation...
0%...10%...40%...70%...80%...100%
Program Operation successful.
INFO: [Xicom 50-44] Elapsed time = 33 sec.
Performing Verify Operation...
0%...10%...20%...30%...40%...50%...60%...70%...80%...90%...100%
INFO: [Xicom 50-44] Elapsed time = 39 sec.
Verify Operation successful.
Flash Operation Successful
4) If I then power cycle board with SD card fitted and have all S1 switches set to OFF position on your TEB0745 development board it fails to boot. NOTE: I still have the CPLD programmed with variant 2
5) If instead, I copy the same BOOT.bin file onto an SD card, set S1-1 to on, power cycle brd then it boots correctly.
I am no expert with the SDK/Vitis tools so am sure I am doing something obviously incorrect. Can you please help me out.
Thanks!
1) I have updated the CPLD to variant 2 allowing JTAG/QSPI/SD Card
2) My main project (bare metal) is using Vivado/Vitis 2024.1 where if I understand your wiki information the Vitis/SDK version has varying degrees of issues when programming the QSPI flash.
3) From this wiki I have installed 2017.2 (seemed the version with the least issues to me) and created an unrelated SDK fsbl application targeting a ZC702 board. I have only done this so that SDK then allows me to use the flash program application. I have then referenced the BOOT.bin file from my 2024.1 project in the flash programming tool and programed/verified successfully. Here is the console op during flashing:
cmd /C program_flash -f \
G:\Vitis_Workspace_2024\SW_Application\BOOT.bin \
-offset 0 -flash_type qspi_single -blank_check -verify -cable type xilinx_tcf url \
TCP:127.0.0.1:3121
****** Xilinx Program Flash
****** Program Flash v2017.2 (64-bit)
**** SW Build 1909853 on Thu Jun 15 18:39:09 MDT 2017
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
Connecting to hw_server @ TCP:127.0.0.1:3121
Connected to hw_server @ TCP:127.0.0.1:3121
Available targets and devices:
Target 0 : jsn-JTAG-ONB4-251633006C35A
Device 0: jsn-JTAG-ONB4-251633006C35A-4ba00477-0
Retrieving Flash info...
Initialization done, programming the memory
BOOT_MODE REG = 0x00000001
WARNING: [Xicom 50-100] The current boot mode is QSPI.
If flash programming fails, configure device for JTAG boot mode and try again.
f probe 0 0 0
Performing Erase Operation...
Erase Operation successful.
INFO: [Xicom 50-44] Elapsed time = 7 sec.
Performing Blank Check Operation...
0%...10%...20%...30%...40%...50%...60%...70%...80%...90%...100%
INFO: [Xicom 50-44] Elapsed time = 39 sec.
Blank Check Operation successful. The part is blank.
Performing Program Operation...
0%...10%...40%...70%...80%...100%
Program Operation successful.
INFO: [Xicom 50-44] Elapsed time = 33 sec.
Performing Verify Operation...
0%...10%...20%...30%...40%...50%...60%...70%...80%...90%...100%
INFO: [Xicom 50-44] Elapsed time = 39 sec.
Verify Operation successful.
Flash Operation Successful
4) If I then power cycle board with SD card fitted and have all S1 switches set to OFF position on your TEB0745 development board it fails to boot. NOTE: I still have the CPLD programmed with variant 2
5) If instead, I copy the same BOOT.bin file onto an SD card, set S1-1 to on, power cycle brd then it boots correctly.
I am no expert with the SDK/Vitis tools so am sure I am doing something obviously incorrect. Can you please help me out.
Thanks!
#10
Trenz Electronic FPGA Modules / Re: TEB0835 Fan Ctrl via LM961...
Last post by StefanK82 - September 13, 2024, 10:06:35 AMMorning everybody,
I solved yesterday's problem myself. My mistake was to rely on the fan's data sheet and take the yellow wire as the PWM signal. This is correct for the fan. But the pinning of the TEB0835 does not reflect this. Long story short, it's just a pinning issue. The pins of the TEB0835 and the KK0835-02 cooling kit do not match. Just swap the blue/yellow cable assignment and everything works like a charm.
Have fun
Stefan
I solved yesterday's problem myself. My mistake was to rely on the fan's data sheet and take the yellow wire as the PWM signal. This is correct for the fan. But the pinning of the TEB0835 does not reflect this. Long story short, it's just a pinning issue. The pins of the TEB0835 and the KK0835-02 cooling kit do not match. Just swap the blue/yellow cable assignment and everything works like a charm.
Have fun
Stefan