Recent Posts

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Trenz Electronic FPGA Modules / Modifying TE0714 to use lower voltage for LVDS
« Last post by mrtn on September 21, 2023, 09:05:44 AM »
Hello,
I have two TE0714-04-52I-7-B boards (3.3V option) with TEBA0714-01 carrier.  I'm using an XMOD JTAG as well.
Wondering if I can manually change out some resistors to turn this into a lower voltage compatible with LVDS differential input and output.  I understand input may work already at 3.3V (with limitations), but LVDS output requires the lower voltage.

Is there any instructions on which resistors to replace?  I see some mention in the schematics but it's unclear what to change.

Thanks for any guidance!  I see the lower voltage boards are generally unavailable or on backorder.
Martin
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Trenz Electronic FPGA Modules / Re: Running NIOSV processor from external SDRAM on Cyclone IV E.
« Last post by Thomas D on September 18, 2023, 11:28:28 AM »
Hi himanshu,
we now have a reference design available online for our TEI0003 CYC1000 board with Nios V/m running through an external SDRAM (Winbond W9864G6JT-6).

The IP Core used is an AXI4 sdram controller from Github. The source code was only slightly adapted for Quartus.

You can simply copy the IP Core and try it out on your board.

br
Thomas
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Trenz Electronic FPGA Modules / Re: Flashing SMF2000's CPU from command-line
« Last post by JH on September 18, 2023, 08:05:23 AM »
Hi,
check JTAG connection between programmer and board.
they must be connected correctly, see:
https://wiki.trenz-electronic.de/display/PD/TE0790+TRM#TE0790TRM-Signals,InterfacesandPins
br
JH
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Trenz Electronic FPGA Modules / Re: Broken JTAG on TE0701-03 / TE0720
« Last post by JH on September 18, 2023, 08:04:07 AM »
Hi,
thanks for your summary feedback. Some small extention.
DIPs on TE0790 depends on power connection, see:
https://wiki.trenz-electronic.de/display/PD/TE0790+TRM#TE0790TRM-Powersupplyoftheadapterboard
https://wiki.trenz-electronic.de/display/PD/TE0790+TRM#TE0790TRM-DIP-switch
br
John
5
UltraScale / Re: TE0807 clock wizard lock failure
« Last post by cs_wiz on September 16, 2023, 08:29:33 AM »
FIXED

This turned out to be a hw issue in the SOM. 02 resistors that act as a potential divider for the reference power line to the GT banks had failed (soldering was damaged). Replaced those resistors and the GT banks are now working as expected.
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Trenz Electronic FPGA Modules / Re: Broken JTAG on TE0701-03 / TE0720
« Last post by mrtn on September 15, 2023, 09:40:16 AM »
If the XMOD EEPROM is erased and you are getting the No devices detected, you can reprogram using a free Xilinx/AMD license.
The procedure for TE0790 XMOD is a bit complicated but here are all the steps:


The XMOD and board should show up in Vivado’s Hardware Manger now.

Initially only seeing connection with DIP 1, 3, 4 all ON and no external power, but in principle only DIP 1 ON, and supplying 3.3v to carrier should work.
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Trenz Electronic FPGA Modules / Re: S7Mini program flash
« Last post by ralblas on September 14, 2023, 01:20:24 PM »
Thanks, that helps, but there are a few things to mention (apart from missing "open_hw_target" in your script).
Programming the flash is only possible with a file with extension .bin.
But write_bitstream only can generate a file with extension .bit.
Just renaming helps, but it's kind of strange; it suggests that another step is needed to convert the .bit file into a .bin file?
Anyway, I did load the renamed file into the flash which did work, after a boot_hw_device it indeed loads the program from flash to fpga.
And it does load the progam from flash after power-up!

Thanks,
Rob.


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Trenz Electronic FPGA Modules / Re: S7Mini program flash
« Last post by Agnesbartlett on September 14, 2023, 08:06:08 AM »
Quote from: Agnesbartlett on September 13, 2023, 02:28:09 PM
Hello,

To load a bitstream into the flash memory of an S7Mini FPGA using a Tcl script in Vivado, you typically follow these steps:

Generate the Bitstream File:

Use Vivado's GUI or Tcl commands to generate the bitstream file (.bit) as you normally would. You mentioned that you can generate a bit file using write_bitstream. This bitstream file is the configuration data that you will eventually load into the flash memory.
Select the Appropriate Flash Device:

In Vivado, select the appropriate flash device for your S7Mini board. You mentioned the n25q64-3.3v-spi-x1_x2_x4 flash device, which seems suitable if it matches the flash chip on your board. Verify this information with your board's documentation.
Initialize the Flash Configuration:

You'll need to initialize the flash memory with the bitstream file. This is typically done using the "Initialize Memory" feature in Vivado. You can use Tcl commands for this purpose.

open_hw
connect_hw_server
current_hw_target [get_hw_targets *]
refresh_hw_device [get_hw_devices]
set_property PROGRAM.FILE [your_bitstream_file.bit] [get_hw_devices [get_property PROGRAM.HW_CFGMEM [get_hw_devices]]]
program_hw_cfgmem -force
Replace [your_bitstream_file.bit] with the path to your generated bitstream file. mcdvoice

Program the Flash:

Use the program_hw_cfgmem Tcl command to program the flash memory with the bitstream.
Verify the Configuration:

After programming the flash, you should verify that the configuration was successful.
Here's a condensed version of the Tcl script:

open_hw
connect_hw_server
current_hw_target [get_hw_targets *]
refresh_hw_device [get_hw_devices]
set_property PROGRAM.FILE [your_bitstream_file.bit] [get_hw_devices [get_property PROGRAM.HW_CFGMEM [get_hw_devices]]]
program_hw_cfgmem -force

Make sure to replace [your_bitstream_file.bit] with the actual path to your bitstream file.


May be this information helps you.



9
UltraScale / TE0807 clock wizard lock failure
« Last post by cs_wiz on September 14, 2023, 07:56:05 AM »
I am working on an SDI passthrough design which requires the utilization of the GT banks for the rx and tx channels and the reference clocks. I found that the pll lock status indicating bit in the cmp_gt_sts[63:0] output signal of the UHDSDI-GT ip indicated a lock failure.

To rule out any error with my SDI design, I generated a much simpler design using clocking wizards (see attached images). The design takes the differential clocks generated by Si5397 on my custom carrier board (later tried with the Si5345 on the SOM as well, same result) and feeds it through the necessary buffers into a clock wizard. I have added counters which are monitored by ILA (these ILAs use a clock generated by the PS). Pin assignments are accurate.

The locked signal of the clock wizard is not asserted and the counters are stuck at zero.

Vitis project has no errors and programs the Si IC without issue. I have verified the clock signals being generated by probing the appropriate capacitors using the oscilloscope.

I tried the same clock wizard design on the ZCU106 board which has the same fpga (xzu7ev). The clock wizard lock signal is asserted and the counters are incremented as expected.

So bottom line, the clock arrives at the fpga without issue but is somehow not detected by the GT banks. I am leaning towards ruling this as an error in the GT banks of the fpga.
Note : The fpga functions perfectly fine for any application that doesnt use GT clocking (UART, Linux build for PS with sample apps, PS ethernet etc.)

Any further tests that I can run to verify whether this is an error in the FPGA? I am looking at purchasing a new SOM if I can verify that is the error. Please let me know if there is anything I may have overlooked.

Am also curious to know whether it is possible for the GT banks to fail (as suspected here) while the fpga functions perfectly fine otherwise. Do share any experience.
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Trenz Electronic FPGA Modules / Re: Flashing SMF2000's CPU from command-line
« Last post by oyousbottom on September 14, 2023, 04:21:00 AM »
I can establish a connection between the TE0790 and the VM using xsdb or xsct, but I am unable to list the targets (the output is shown below).
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