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Quote from: JH on June 02, 2025, 08:50:31 AMHi,
bitstream itself does not configure PS. This will be done by FSBL, not with bitstream.This is the reason why you didn't see any VIO core, because CLK is missing. In case you want to use PS-PL CLKs and you need only PL part, boot system with your configured PS from SD Card (You can use our prebuilt Boot.bin in case you use the same CLKs like we in our reference design) and overwrite PL over JTAG like you has done above.
br
John
Quote from: Antti Lukats on June 05, 2025, 10:16:45 AMHi,
all you need is to read the TE0701 TRM, it is all explained there:
https://wiki.trenz-electronic.de/display/PD/TE0701+TRM
There is a diagram that shows that the CPLD is "forwarding" the UART pins, and a bit later is defined to WHAT pins the forwarding is done. So all the information you need is there.
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