Recent Posts

Pages: [1] 2 3 ... 10
1
UltraScale / Re: Trying to flash QSPI over JTAG on TE0703 + TE0720 -
« Last post by JH on Today at 06:53:43 AM »
Hi,
can you send me the serial number of your TE0720. It's on the white sticker with QR code on the module(I just want to make sure that you have TE0720-03-2IF).

Please download newest version of the Testboard Reference design:
https://wiki.trenz-electronic.de/display/PD/TE0720+Test+Board
https://wiki.trenz-electronic.de/display/PD/TE0720+Test+Board#TE0720TestBoard-Download

--> use this one with prebuilt binaries.
For  TE0720-03-2IF use
./prebuilt/boot_images/2if_1gb/u-boot/Boot.bin
./prebuilt/os/petalinux/1GB/image.ub
./prebuilt/os/petalinux/1GB/boot.scr

and put the on a SD with on fat32 partition and boot from SD.
--> Set TE0703 DIP to
S2-1:ON (it's normally no matter, it activate/deactivate SD CD Pin usage)
S2-2:ON -->Xilinx SoC is in the JTAG Chain, otherwise you see the CPLD of the modul if S2-3 is also ON
S2-3:ON --> Module is in the JTAG chain, otherwise you see the CPLD of the carrier
S2-4:ON --> Boot from SD, otherwise Boot from QSPI
see: https://wiki.trenz-electronic.de/display/PD/TE0703+TRM#TE0703TRM-DIPswitches

For UART use for example putty (it goes over the same USB cable like JTAG) for configuration, see:
https://wiki.trenz-electronic.de/display/PD/TE0720+Test+Board#TE0720TestBoard-Usage
https://wiki.trenz-electronic.de/display/PD/Reference+Designs+with+PetaLinux

This should boot completely. Please send me one time the whole boot log

After seeing the boot log, let's look at your flash programming problem.

PS: Do not use SDSoC_PFM_TE0720-03-2IF_20181105171203.zip, it was for Xilinx SDSoC software which Xilinx has discontinued and integrated the functionality into vitis AI.


br
John


2
UltraScale / Re: Trying to flash QSPI over JTAG on TE0703 + TE0720 -
« Last post by Aaron on December 02, 2021, 05:25:06 PM »
Thank you for your reply.  I really appreciate that you monitor the forums and respond promptly to all us noobs :)

It is a TE0720-03-2IF, I believe, though I don't believe it is visible on the part itself.  The FSBL has some extra debug enabled, and it prints out:

SoM: TE0720-03-1A  F SC REV:05

(I do not see a -1A listed on the TE0720 product page, so I assume this really means something else)

You ask if my PS configuration is correct:  I did not know there is a correct software configuration for JTAG booting.  Do you mean something has to change in my software?  My only experience is with the ZynqMP products we have used in the past (both Xilinx ZynqMP and Trenz TE0808), where a platform that was normally booting from QSPI flash could be modified with a single jumper that would change its boot mode register value, thus preparing it to be flashed over JTAG using XSDK (with a zynqmp_fsbl.elf).  That is what I am looking for here - an equivalent with the zynq7.  However, the only switch I see is SW2-4, which only allows two boot modes:  SD or QSPI.

I am hoping there is a "jumper only"  solution to flash the TE0720 using PC software such as the XSDK or program_flash.  Is this possible? 

In the TRM, I see only SW-2-4 has SD and QSPI boot mode. No JTAG.  I see some other switches that are described as related to JTAG, but some seem to suggest it will program the CPLD.  Bricking the CPLD would not be my first choice, so I thought I'd ask.  Once again:  are there any switches or jumpers on TE0703-06 that can put the Zynq SoM into JTAG boot mode, so it will sit and wait for a JTAG connection so it can be flashed over JTAG?

In the case boot mode != JTAG, I understand you are saying one needs a special FSBL, but I would very much like to know how to make boot mode == JTAG.  This my only question.  I tried using your prebuilt zynq_fsbl.elf vs mine (generated in petalinux), but I don't see a difference.  In each case, the Trenz starts booting from the SD while the XSDK is trying to flash, and the flash ends up failing.

I tried downloading "SDSoC_PFM_TE0720-03-2IF_20181105171203.zip", but there does not appear to be anything bootable in there - at least, nothing that gave me any console output once I put the TE0703 into SD boot mode and power-cycled.

1) I removed my BOOT.BIN and image.ub from the SD card
2) I copied sw\Linux\Linux\image\image.ub to the top directory of my SD card
3) I copied sw\Linux\boot\* (linux.bif, u-boot.elf, and zynq_fsbl.elf) to the top directory of the SD card

The result of powering on was a dead console.  Are there other files I should have copied?

Also, I noticed that when I try flashing with boot mode == SD, the platform resets and begins booting the linux image on the SD, but stops short of starting the kernel.  This is why the XSDK fails to flash, I believe - the Zynq is still trying to boot while the XSDK is flashing.  What appears to be needed is a way to halt the boot process , such as a jumper that will force the zynq to wait for a jtag connection.

Code: [Select]
Available targets and devices:
Target 0 : jsn-JTAG-ONB4-251633000000A
Device 0: jsn-JTAG-ONB4-251633000000A-4ba00477-0

Retrieving Flash info...

Initialization done, programming the memory
===== mrd->addr=0xF800025C, data=0x00000005 =====
BOOT_MODE REG = 0x00000005
WARNING: [Xicom 50-100] The current boot mode is SD.
If flash programming fails, configure device for JTAG boot mode and try again.
Downloading FSBL...
Running FSBL...
Finished running FSBL.

One more thing I will try is getting a new set of TE0703, TE0720 and microSD card from unopened boxes I have, since the SD card I am using was previously corrupted and then partitioned, and the TE0703 power connector or its power cable is starting to disconnect power when it is wiggled (the black plastic connector looks like it moves upward and away from the 0703 PCB when upward pressure is placed on the AC plug).  So the circuitry is frequently seeing power being turned off and on quickly whenever the cable is wiggled and I'm sure that is not good.

Thanks
Aaron
3
Trenz Electronic FPGA Modules / Re: One-Wire Interace for MAC-ID chip on TE0710
« Last post by toka on December 02, 2021, 12:44:09 PM »
As a suggestion: I just created a custom AXI peripheral to read out the vector.
4
Trenz Electronic FPGA Modules / Re: One-Wire Interace for MAC-ID chip on TE0710
« Last post by Antti Lukats on December 02, 2021, 09:11:39 AM »
same eeprom so yes suitable IP. The address location is defined in device datasheet but you do not need to know it, the IP core has fixed address for readout. The IP reads the mac and returns a vector, you need to add some "register read" IP to the bus in order to access it from freeRTOS.
5
UltraScale / Re: Trying to flash QSPI over JTAG on TE0703 + TE0720 -
« Last post by JH on December 02, 2021, 08:00:24 AM »
Hi,
can you tell me which TE0720 assembly variant you has?

Did you use correct PS configuration?
For Vivado 2018.2, you need also special FSBL for flash configuration in case Boot mode is != JTAG. We provide one in our reference design or you can create own one.
https://wiki.trenz-electronic.de/pages/viewpage.action?pageId=105689937
--> https://www.xilinx.com/support/answers/70148.html

Can you also start prebuilt Linux binaries from our reference design and check if flash is detected there correctly
https://wiki.trenz-electronic.de/display/PD/TE0720+Test+Board
br
John
6
UltraScale / Trying to flash QSPI over JTAG on TE0703 + TE0720 -
« Last post by Aaron on December 02, 2021, 12:03:17 AM »
I would like to flash this device using a PC running XSDK 2018.2.  However, the flash complains that boot mode is SD or QSPI (depending on SW2-4), but should be JTAG.  However, the TRM says nothing about a JTAG boot mode.

Is there such a thing as a jtag boot mode on this device?  If so, please help me in the future by pointing to where I missed reference to it in the TRM.

Here are some more details, if needed:
When I flash, I select qspi_dual_parallel.  In SD mode, the flash will complete, but fail when it attempts to check the data.

In QSPI boot mode, a few times, it complained "SF:  Unrecognized JEDEC code".  Another time it hung.  Here is the log of the JEDEC error:

Code: [Select]
Model: Zynq CSE QSPI Board
Board: Xilinx Zynq
Silicon: v3.1
DRAM:  256 KiB
WARNING: Caches not enabled
Using default environment

In:    dcc
Out:   dcc
Err:   dcc

Zynq> sf probe 0 0 0
SF: unrecognized JEDEC id bytes: 00, 00, 00
Failed to initialize SPI flash at 0:0 (error -2)
Zynq> ERROR: [Xicom 50-186] Error while detecting SPI flash device - unrecognized JEDEC id bytes: 00, 00, 00
Problem in running uboot
Flash programming initialization failed.
ERROR: Flash Operation Failed

Any advice would be welcome.

7
Trenz Electronic FPGA Modules / Re: One-Wire Interace for MAC-ID chip on TE0710
« Last post by danvp on December 01, 2021, 04:14:00 PM »
Hello Antti Lukats,

I need to read the MAC from the EEPROM in the TE0712, from freeRTOS.

Looking for info I bumped into this post. Is the IP for the MAC ID EEPROM that you shared with toka also suitable for the TE0712?

And if it is suitable, can you please also offer some guidance on how to read the MAC? Where in the EEPROM is it stored?

Thanks a lot in advance,

danvp
8
Trenz Electronic FPGA Modules / Re: PS-GTR Transceiver on TE0808-5
« Last post by JH on December 01, 2021, 12:51:10 PM »
Hi,

Quote
We just wanted to eliminate the HW as source of the Failure with a PS-GTR Connection.
Yes, it always makes sense to look for all possible causes of errors. But next time maybe also explain how you has connect in on your carrier, when you ask such a question. TE0808 simple routed the GTR to the B2B connector without any predefined usage.

Quote
In the meanwhile our Software guys found the bugs in their mapping of the transceiver Clock. And the Interface is now working correct.
There are clearly too many ways that such interfaces don't work properly these days. 

It's good to hear that you get it working on your place.

br
John
9
Trenz Electronic FPGA Modules / Re: PS-GTR Transceiver on TE0808-5
« Last post by Manuel on December 01, 2021, 12:43:00 PM »
Thanks for Your Answer.
We just wanted to eliminate the HW as source of the Failure with a PS-GTR Connection.
In the meanwhile our Software guys found the bugs in their mapping of the transceiver Clock. And the Interface is now working correct.
10
Trenz Electronic FPGA Modules / Re: PS-GTR Transceiver on TE0808-5
« Last post by JH on December 01, 2021, 12:07:25 PM »
Hi,
I don't know what you mean with everything is prepared like on the Xilinx ZynqMP pictures.

GTR are connected and powered on TE0808, see schematics:
https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0808/REV05/Documents
Reference CLK depends on your carrier. You can either configure TE0808 on board PLL (wihich must be configured via I2C or write NVM one time over I2C) or use external GTR REF CLK which are need for optical ETH.

"optical Ethernet" is a wide range and depends on a lot of configurations.
We used GTR on TE0808 at the moment only for PCIe, USB3, SATA and DP together with TEBF0808

br
John
 
Pages: [1] 2 3 ... 10