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Quartus Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Start of session at: Tue Aug 18 2020 10:02:46
Current directory: C:/data/Manufucture/Quartus/19.1/test_board
Log file: C:/data/Manufucture/Quartus/19.1/test_board/log/quartus_20200818-100246.log
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Info: (TE) Load Utilities script finished
Info: (TE) Load Settings Script finished
Info: (TE) Load Quartus script finished
Info: (TE) Load sdk script finished
Info: (TE) Load designs script finished
Info: (TE) Load export script finished
Info: [TE_MAIN-02] (TE) Load sys_pjc script finished
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Info: [TE_INIT-01] Board Part definition:
::TE::BASEFOLDER: C:/data/Manufucture/Quartus/19.1/test_board
::TE::QPROJ_PATH: C:/data/Manufucture/Quartus/19.1/test_board/quartus
::TE::BOARDDEF_PATH: C:/data/Manufucture/Quartus/19.1/test_board/board_files
::TE::PREBUILT_PATH: C:/data/Manufucture/Quartus/19.1/test_board/prebuilt
::TE::SOURCE_PATH: C:/data/Manufucture/Quartus/19.1/test_board/source_files
::TE::QPROJ_SOURCE_PATH: C:/data/Manufucture/Quartus/19.1/test_board/source_files/quartus
::TE::SDK_SOURCE_PATH: C:/data/Manufucture/Quartus/19.1/test_board/source_files/software
::TE::LOG_PATH: C:/data/Manufucture/Quartus/19.1/test_board/log
::TE::SDK_PATH: C:/data/Manufucture/Quartus/19.1/test_board/software
::TE::BACKUP_PATH: C:/data/Manufucture/Quartus/19.1/test_board/backup
::TE::SET_PATH: C:/data/Manufucture/Quartus/19.1/test_board/settings
::TE::COMMAND_SHELL_PATH: wsl bash {[exec wsl wslpath c:/intelfpga_lite/19.1/quartus/../nios2eds/]nios2_command_shell.sh}
::TE::QROOTPATH: c:/intelfpga_lite/19.1/quartus/
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Info: [TE_INIT-15] Supported quartus version: 19.1.0 Lite. Used quartus version: 19.1.0 Lite.
Info: [TE_INIT-17] Used platform: windows
Info: [TE_INIT-20] Used linux distribution for WSL:
NAME STATE VERSION
* Ubuntu-18.04 Stopped 2
Info: [TE_INIT-05] Read ZIP ignore list (File: C:/data/Manufucture/Quartus/19.1/test_board/settings/zip_ignore_list.csv).
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Info: (TE) Load TK script finished
Info: [TE_TK-01] Start 'Create Project' GUI. Change to GUI.
Info: [TE_TK-03] Selected Product ID: TEI0001-02-08-C8
Info: [TE_TK-10] Start creating project.
Info: [TE_DES-2] Run TE::INIT::run_project 1 1 0 3
Info: [TE_UTILS-06] Clean project workspace
Info: [TE_UTILS-08] C:/data/Manufucture/Quartus/19.1/test_board/quartus deleted.
Info: [TE_UTILS-10] Clean software workspace
Info: [TE_UTILS-12] C:/data/Manufucture/Quartus/19.1/test_board/software deleted.
Info: [TE_INIT-09] Board Part definition:
::TE::ID: 1
::TE::PRODID: TEI0001-02-08-C8
::TE::FAMILY: MAX 10
::TE::DEVICE: 10M08SAU169C8G
::TE::SHORTNAME: 08_C8_8MB
::TE::FLASHTYP: onchip
::TE::FLASH_SIZE: NA
::TE::DDR_DEV: TEI0001_single_W9864G6JT-6
::TE::DDR_SIZE: 8MB
::TE::PCB_REV: REV02
::TE::NOTES: NA
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Info: [TE_INIT-13] Use quartus source files from C:/data/Manufucture/Quartus/19.1/test_board/source_files/quartus
Info: [TE_INIT-14] Use software source files from C:/data/Manufucture/Quartus/19.1/test_board/source_files/software
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Info: [TE_DES-25] Run build project (all). Please wait ...
Info: [TE_QUART-13] Create empty project. Please wait ...
Info: [TE_QUART-14] Create empty project -> done
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Info: [TE_UTILS-26] Copy source files to project ...
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Info: [TE_UTILS-30] Modify files. Please wait ...
Info: [TE_INIT-10] Read qsys modify list (File: C:/data/Manufucture/Quartus/19.1/test_board/settings/mod_list.csv).
Info: >> read NIOS_test_board.tcl {}
Info: >> 0 {*set_project_property DEVICE_FAMILY {*}} {set_project_property DEVICE_FAMILY $device_family}
Info: >> 0 {*set_project_property DEVICE {*}} {set_project_property DEVICE $device}
Info: >> 1 *save_system* auto_assign_system_base_addresses
Info: >> 2 *create_system* {set arg [split $::args "|"]} {set device [lindex $arg 0]} {set device_family [lindex $arg 1]} {set ddr_device [lindex $arg 2]}
Info: >> 3 sdram_controller *
Info: >> 4 sdram_controller {apply_preset sdram_controller "$ddr_device"}
Info: >> write NIOS_test_board.tcl { }
Info: >> read test_board.tcl {}
Info: >> 0 {* -name DEVICE *} NA
Info: >> 0 {* -name FAMILY *} NA
Info: >> write test_board.tcl {}
Info: [TE_UTILS-31] Modify files -> done
Info: [TE_QUART-01] Create qsys. It can take a few minutes, please wait ...
Info: [TE_QUART-02] Command results on: exec c:/intelfpga_lite/19.1/quartus/sopc_builder/bin/qsys-script.exe {--cmd=set ::args 10M08SAU169C8G|MAX\ 10|TEI0001_single_W9864G6JT-6} --script=C:/data/Manufucture/Quartus/19.1/test_board/quartus/NIOS_test_board.tcl {--search-path=C:/data/Manufucture/Quartus/19.1/test_board/quartus/ip/**/*,C:/data/Manufucture/Quartus/19.1/test_board/settings/*,$}:
Info: Doing: qsys-script --cmd=set ::args 10M08SAU169C8G|MAX\ 10|TEI0001_single_W9864G6JT-6 --script=C:/data/Manufucture/Quartus/19.1/test_board/quartus/NIOS_test_board.tcl --search-path=C:/data/Manufucture/Quartus/19.1/test_board/quartus/ip/**/*,C:/data/Manufucture/Quartus/19.1/test_board/settings/*,$
Info: create_system NIOS_test_board
Info: set_project_property DEVICE_FAMILY MAX 10
Info: Info: The device and speed grade changed to the defaults of the device_family MAX 10.
Info: set_project_property DEVICE 10M08SAU169C8G
Info: set_project_property HIDE_FROM_IP_CATALOG false
Info: add_instance clk clock_source 19.1
Info: set_instance_parameter_value clk clockFrequency 12000000.0
Info: set_instance_parameter_value clk clockFrequencyKnown 1
Info: set_instance_parameter_value clk resetSynchronousEdges NONE
Info: add_instance nios2 altera_nios2_gen2 19.1
Info: set_instance_parameter_value nios2 bht_ramBlockType Automatic
Info: set_instance_parameter_value nios2 breakOffset 32
Info: set_instance_parameter_value nios2 breakSlave None
Info: set_instance_parameter_value nios2 cdx_enabled 0
Info: set_instance_parameter_value nios2 cpuArchRev 1
Info: set_instance_parameter_value nios2 cpuID 0
Info: set_instance_parameter_value nios2 cpuReset 0
Info: set_instance_parameter_value nios2 data_master_high_performance_paddr_base 0
Info: set_instance_parameter_value nios2 data_master_high_performance_paddr_size 0.0
Info: set_instance_parameter_value nios2 data_master_paddr_base 0
Info: set_instance_parameter_value nios2 data_master_paddr_size 0.0
Info: set_instance_parameter_value nios2 dcache_bursts false
Info: set_instance_parameter_value nios2 dcache_numTCDM 0
Info: set_instance_parameter_value nios2 dcache_ramBlockType Automatic
Info: set_instance_parameter_value nios2 dcache_size 2048
Info: set_instance_parameter_value nios2 dcache_tagramBlockType Automatic
Info: set_instance_parameter_value nios2 dcache_victim_buf_impl ram
Info: set_instance_parameter_value nios2 debug_OCIOnchipTrace _128
Info: set_instance_parameter_value nios2 debug_assignJtagInstanceID 0
Info: set_instance_parameter_value nios2 debug_datatrigger 0
Info: set_instance_parameter_value nios2 debug_debugReqSignals 0
Info: set_instance_parameter_value nios2 debug_enabled 1
Info: set_instance_parameter_value nios2 debug_hwbreakpoint 0
Info: set_instance_parameter_value nios2 debug_jtagInstanceID 0
Info: set_instance_parameter_value nios2 debug_traceStorage onchip_trace
Info: set_instance_parameter_value nios2 debug_traceType none
Info: set_instance_parameter_value nios2 debug_triggerArming 1
Info: set_instance_parameter_value nios2 dividerType no_div
Info: set_instance_parameter_value nios2 exceptionOffset 32
Info: set_instance_parameter_value nios2 exceptionSlave sdram_controller.s1
Info: set_instance_parameter_value nios2 fa_cache_line 2
Info: set_instance_parameter_value nios2 fa_cache_linesize 0
Info: set_instance_parameter_value nios2 flash_instruction_master_paddr_base 0
Info: set_instance_parameter_value nios2 flash_instruction_master_paddr_size 0.0
Info: set_instance_parameter_value nios2 icache_burstType None
Info: set_instance_parameter_value nios2 icache_numTCIM 0
Info: set_instance_parameter_value nios2 icache_ramBlockType Automatic
Info: set_instance_parameter_value nios2 icache_size 4096
Info: set_instance_parameter_value nios2 icache_tagramBlockType Automatic
Info: set_instance_parameter_value nios2 impl Tiny
Info: set_instance_parameter_value nios2 instruction_master_high_performance_paddr_base 0
Info: set_instance_parameter_value nios2 instruction_master_high_performance_paddr_size 0.0
Info: set_instance_parameter_value nios2 instruction_master_paddr_base 0
Info: set_instance_parameter_value nios2 instruction_master_paddr_size 0.0
Info: set_instance_parameter_value nios2 io_regionbase 0
Info: set_instance_parameter_value nios2 io_regionsize 0
Info: set_instance_parameter_value nios2 master_addr_map 0
Info: set_instance_parameter_value nios2 mmu_TLBMissExcOffset 0
Info: set_instance_parameter_value nios2 mmu_TLBMissExcSlave None
Info: set_instance_parameter_value nios2 mmu_autoAssignTlbPtrSz 1
Info: set_instance_parameter_value nios2 mmu_enabled 0
Info: set_instance_parameter_value nios2 mmu_processIDNumBits 8
Info: set_instance_parameter_value nios2 mmu_ramBlockType Automatic
Info: set_instance_parameter_value nios2 mmu_tlbNumWays 16
Info: set_instance_parameter_value nios2 mmu_tlbPtrSz 7
Info: set_instance_parameter_value nios2 mmu_udtlbNumEntries 6
Info: set_instance_parameter_value nios2 mmu_uitlbNumEntries 4
Info: set_instance_parameter_value nios2 mpu_enabled 0
Info: set_instance_parameter_value nios2 mpu_minDataRegionSize 12
Info: set_instance_parameter_value nios2 mpu_minInstRegionSize 12
Info: set_instance_parameter_value nios2 mpu_numOfDataRegion 8
Info: set_instance_parameter_value nios2 mpu_numOfInstRegion 8
Info: set_instance_parameter_value nios2 mpu_useLimit 0
Info: set_instance_parameter_value nios2 mpx_enabled 0
Info: set_instance_parameter_value nios2 mul_32_impl 2
Info: set_instance_parameter_value nios2 mul_64_impl 0
Info: set_instance_parameter_value nios2 mul_shift_choice 0
Info: set_instance_parameter_value nios2 ocimem_ramBlockType Automatic
Info: set_instance_parameter_value nios2 ocimem_ramInit 0
Info: set_instance_parameter_value nios2 regfile_ramBlockType Automatic
Info: set_instance_parameter_value nios2 register_file_por 0
Info: set_instance_parameter_value nios2 resetOffset 0
Info: set_instance_parameter_value nios2 resetSlave onchip_flash.data
Info: set_instance_parameter_value nios2 resetrequest_enabled 1
Info: set_instance_parameter_value nios2 setting_HBreakTest 0
Info: set_instance_parameter_value nios2 setting_HDLSimCachesCleared 1
Info: set_instance_parameter_value nios2 setting_activateMonitors 1
Info: set_instance_parameter_value nios2 setting_activateTestEndChecker 0
Info: set_instance_parameter_value nios2 setting_activateTrace 0
Info: set_instance_parameter_value nios2 setting_allow_break_inst 0
Info: set_instance_parameter_value nios2 setting_alwaysEncrypt 1
Info: set_instance_parameter_value nios2 setting_asic_add_scan_mode_input 0
Info: set_instance_parameter_value nios2 setting_asic_enabled 0
Info: set_instance_parameter_value nios2 setting_asic_synopsys_translate_on_off 0
Info: set_instance_parameter_value nios2 setting_asic_third_party_synthesis 0
Info: set_instance_parameter_value nios2 setting_avalonDebugPortPresent 0
Info: set_instance_parameter_value nios2 setting_bhtPtrSz 8
Info: set_instance_parameter_value nios2 setting_bigEndian 0
Info: set_instance_parameter_value nios2 setting_branchpredictiontype Dynamic
Info: set_instance_parameter_value nios2 setting_breakslaveoveride 0
Info: set_instance_parameter_value nios2 setting_clearXBitsLDNonBypass 1
Info: set_instance_parameter_value nios2 setting_dc_ecc_present 1
Info: set_instance_parameter_value nios2 setting_disable_tmr_inj 0
Info: set_instance_parameter_value nios2 setting_disableocitrace 0
Info: set_instance_parameter_value nios2 setting_dtcm_ecc_present 1
Info: set_instance_parameter_value nios2 setting_ecc_present 0
Info: set_instance_parameter_value nios2 setting_ecc_sim_test_ports 0
Info: set_instance_parameter_value nios2 setting_exportHostDebugPort 0
Info: set_instance_parameter_value nios2 setting_exportPCB 0
Info: set_instance_parameter_value nios2 setting_export_large_RAMs 0
Info: set_instance_parameter_value nios2 setting_exportdebuginfo 0
Info: set_instance_parameter_value nios2 setting_exportvectors 0
Info: set_instance_parameter_value nios2 setting_fast_register_read 0
Info: set_instance_parameter_value nios2 setting_ic_ecc_present 1
Info: set_instance_parameter_value nios2 setting_interruptControllerType Internal
Info: set_instance_parameter_value nios2 setting_itcm_ecc_present 1
Info: set_instance_parameter_value nios2 setting_mmu_ecc_present 1
Info: set_instance_parameter_value nios2 setting_oci_export_jtag_signals 0
Info: set_instance_parameter_value nios2 setting_oci_version 1
Info: set_instance_parameter_value nios2 setting_preciseIllegalMemAccessException 0
Info: set_instance_parameter_value nios2 setting_removeRAMinit 0
Info: set_instance_parameter_value nios2 setting_rf_ecc_present 1
Info: set_instance_parameter_value nios2 setting_shadowRegisterSets 0
Info: set_instance_parameter_value nios2 setting_showInternalSettings 0
Info: set_instance_parameter_value nios2 setting_showUnpublishedSettings 0
Info: set_instance_parameter_value nios2 setting_support31bitdcachebypass 1
Info: set_instance_parameter_value nios2 setting_tmr_output_disable 0
Info: set_instance_parameter_value nios2 setting_usedesignware 0
Info: set_instance_parameter_value nios2 shift_rot_impl 1
Info: set_instance_parameter_value nios2 tightly_coupled_data_master_0_paddr_base 0
Info: set_instance_parameter_value nios2 tightly_coupled_data_master_0_paddr_size 0.0
Info: set_instance_parameter_value nios2 tightly_coupled_data_master_1_paddr_base 0
Info: set_instance_parameter_value nios2 tightly_coupled_data_master_1_paddr_size 0.0
Info: set_instance_parameter_value nios2 tightly_coupled_data_master_2_paddr_base 0
Info: set_instance_parameter_value nios2 tightly_coupled_data_master_2_paddr_size 0.0
Info: set_instance_parameter_value nios2 tightly_coupled_data_master_3_paddr_base 0
Info: set_instance_parameter_value nios2 tightly_coupled_data_master_3_paddr_size 0.0
Info: set_instance_parameter_value nios2 tightly_coupled_instruction_master_0_paddr_base 0
Info: set_instance_parameter_value nios2 tightly_coupled_instruction_master_0_paddr_size 0.0
Info: set_instance_parameter_value nios2 tightly_coupled_instruction_master_1_paddr_base 0
Info: set_instance_parameter_value nios2 tightly_coupled_instruction_master_1_paddr_size 0.0
Info: set_instance_parameter_value nios2 tightly_coupled_instruction_master_2_paddr_base 0
Info: set_instance_parameter_value nios2 tightly_coupled_instruction_master_2_paddr_size 0.0
Info: set_instance_parameter_value nios2 tightly_coupled_instruction_master_3_paddr_base 0
Info: set_instance_parameter_value nios2 tightly_coupled_instruction_master_3_paddr_size 0.0
Info: set_instance_parameter_value nios2 tmr_enabled 0
Info: set_instance_parameter_value nios2 tracefilename
Info: set_instance_parameter_value nios2 userDefinedSettings
Info: add_instance onchip_flash altera_onchip_flash 19.1
Info: set_instance_parameter_value onchip_flash CLOCK_FREQUENCY 116.0
Info: set_instance_parameter_value onchip_flash CONFIGURATION_MODE Single Uncompressed Image with Memory Initialization
Info: set_instance_parameter_value onchip_flash CONFIGURATION_SCHEME Internal Configuration
Info: set_instance_parameter_value onchip_flash DATA_INTERFACE Parallel
Info: set_instance_parameter_value onchip_flash READ_BURST_COUNT 8
Info: set_instance_parameter_value onchip_flash READ_BURST_MODE Incrementing
Info: set_instance_parameter_value onchip_flash SECTOR_ACCESS_MODE Read\ and\ write Read\ and\ write Read\ and\ write Read\ and\ write Read\ and\ write
Info: set_instance_parameter_value onchip_flash initFlashContent 1
Info: set_instance_parameter_value onchip_flash initializationFileName ../software/test_board/mem_init/onchip_flash.hex
Info: set_instance_parameter_value onchip_flash initializationFileNameForSim
Info: set_instance_parameter_value onchip_flash useNonDefaultInitFile 1
Info: add_instance pio_led altera_avalon_pio 19.1
Info: set_instance_parameter_value pio_led bitClearingEdgeCapReg 0
Info: set_instance_parameter_value pio_led bitModifyingOutReg 0
Info: set_instance_parameter_value pio_led captureEdge 0
Info: set_instance_parameter_value pio_led direction Output
Info: set_instance_parameter_value pio_led edgeType RISING
Info: set_instance_parameter_value pio_led generateIRQ 0
Info: set_instance_parameter_value pio_led irqType LEVEL
Info: set_instance_parameter_value pio_led resetValue 0.0
Info: set_instance_parameter_value pio_led simDoTestBenchWiring 0
Info: set_instance_parameter_value pio_led simDrivenValue 0.0
Info: set_instance_parameter_value pio_led width 8
Info: add_instance pio_mode altera_avalon_pio 19.1
Info: set_instance_parameter_value pio_mode bitClearingEdgeCapReg 0
Info: set_instance_parameter_value pio_mode bitModifyingOutReg 0
Info: set_instance_parameter_value pio_mode captureEdge 0
Info: set_instance_parameter_value pio_mode direction Input
Info: set_instance_parameter_value pio_mode edgeType RISING
Info: set_instance_parameter_value pio_mode generateIRQ 0
Info: set_instance_parameter_value pio_mode irqType LEVEL
Info: set_instance_parameter_value pio_mode resetValue 0.0
Info: set_instance_parameter_value pio_mode simDoTestBenchWiring 0
Info: set_instance_parameter_value pio_mode simDrivenValue 0.0
Info: set_instance_parameter_value pio_mode width 3
Info: add_instance pll altpll 19.1
Info: set_instance_parameter_value pll AVALON_USE_SEPARATE_SYSCLK NO
Info: set_instance_parameter_value pll BANDWIDTH
Info: set_instance_parameter_value pll BANDWIDTH_TYPE AUTO
Info: set_instance_parameter_value pll CLK0_DIVIDE_BY 6
Info: set_instance_parameter_value pll CLK0_DUTY_CYCLE 50
Info: set_instance_parameter_value pll CLK0_MULTIPLY_BY 25
Info: set_instance_parameter_value pll CLK0_PHASE_SHIFT 0
Info: set_instance_parameter_value pll CLK1_DIVIDE_BY 6
Info: set_instance_parameter_value pll CLK1_DUTY_CYCLE 50
Info: set_instance_parameter_value pll CLK1_MULTIPLY_BY 25
Info: set_instance_parameter_value pll CLK1_PHASE_SHIFT -5000
Info: set_instance_parameter_value pll CLK2_DIVIDE_BY
Info: set_instance_parameter_value pll CLK2_DUTY_CYCLE
Info: set_instance_parameter_value pll CLK2_MULTIPLY_BY
Info: set_instance_parameter_value pll CLK2_PHASE_SHIFT
Info: set_instance_parameter_value pll CLK3_DIVIDE_BY
Info: set_instance_parameter_value pll CLK3_DUTY_CYCLE
Info: set_instance_parameter_value pll CLK3_MULTIPLY_BY
Info: set_instance_parameter_value pll CLK3_PHASE_SHIFT
Info: set_instance_parameter_value pll CLK4_DIVIDE_BY
Info: set_instance_parameter_value pll CLK4_DUTY_CYCLE
Info: set_instance_parameter_value pll CLK4_MULTIPLY_BY
Info: set_instance_parameter_value pll CLK4_PHASE_SHIFT
Info: set_instance_parameter_value pll CLK5_DIVIDE_BY
Info: set_instance_parameter_value pll CLK5_DUTY_CYCLE
Info: set_instance_parameter_value pll CLK5_MULTIPLY_BY
Info: set_instance_parameter_value pll CLK5_PHASE_SHIFT
Info: set_instance_parameter_value pll CLK6_DIVIDE_BY
Info: set_instance_parameter_value pll CLK6_DUTY_CYCLE
Info: set_instance_parameter_value pll CLK6_MULTIPLY_BY
Info: set_instance_parameter_value pll CLK6_PHASE_SHIFT
Info: set_instance_parameter_value pll CLK7_DIVIDE_BY
Info: set_instance_parameter_value pll CLK7_DUTY_CYCLE
Info: set_instance_parameter_value pll CLK7_MULTIPLY_BY
Info: set_instance_parameter_value pll CLK7_PHASE_SHIFT
Info: set_instance_parameter_value pll CLK8_DIVIDE_BY
Info: set_instance_parameter_value pll CLK8_DUTY_CYCLE
Info: set_instance_parameter_value pll CLK8_MULTIPLY_BY
Info: set_instance_parameter_value pll CLK8_PHASE_SHIFT
Info: set_instance_parameter_value pll CLK9_DIVIDE_BY
Info: set_instance_parameter_value pll CLK9_DUTY_CYCLE
Info: set_instance_parameter_value pll CLK9_MULTIPLY_BY
Info: set_instance_parameter_value pll CLK9_PHASE_SHIFT
Info: set_instance_parameter_value pll COMPENSATE_CLOCK CLK0
Info: set_instance_parameter_value pll DOWN_SPREAD
Info: set_instance_parameter_value pll DPA_DIVIDER
Info: set_instance_parameter_value pll DPA_DIVIDE_BY
Info: set_instance_parameter_value pll DPA_MULTIPLY_BY
Info: set_instance_parameter_value pll ENABLE_SWITCH_OVER_COUNTER
Info: set_instance_parameter_value pll EXTCLK0_DIVIDE_BY
Info: set_instance_parameter_value pll EXTCLK0_DUTY_CYCLE
Info: set_instance_parameter_value pll EXTCLK0_MULTIPLY_BY
Info: set_instance_parameter_value pll EXTCLK0_PHASE_SHIFT
Info: set_instance_parameter_value pll EXTCLK1_DIVIDE_BY
Info: set_instance_parameter_value pll EXTCLK1_DUTY_CYCLE
Info: set_instance_parameter_value pll EXTCLK1_MULTIPLY_BY
Info: set_instance_parameter_value pll EXTCLK1_PHASE_SHIFT
Info: set_instance_parameter_value pll EXTCLK2_DIVIDE_BY
Info: set_instance_parameter_value pll EXTCLK2_DUTY_CYCLE
Info: set_instance_parameter_value pll EXTCLK2_MULTIPLY_BY
Info: set_instance_parameter_value pll EXTCLK2_PHASE_SHIFT
Info: set_instance_parameter_value pll EXTCLK3_DIVIDE_BY
Info: set_instance_parameter_value pll EXTCLK3_DUTY_CYCLE
Info: set_instance_parameter_value pll EXTCLK3_MULTIPLY_BY
Info: set_instance_parameter_value pll EXTCLK3_PHASE_SHIFT
Info: set_instance_parameter_value pll FEEDBACK_SOURCE
Info: set_instance_parameter_value pll GATE_LOCK_COUNTER
Info: set_instance_parameter_value pll GATE_LOCK_SIGNAL
Info: set_instance_parameter_value pll HIDDEN_CONSTANTS CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 25 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 25 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 83333 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT -5000 CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 6 CT#CLK1_DIVIDE_BY 6 CT#PORT_LOCKED PORT_UNUSED
Info: set_instance_parameter_value pll HIDDEN_CUSTOM_ELABORATION altpll_avalon_elaboration
Info: set_instance_parameter_value pll HIDDEN_CUSTOM_POST_EDIT altpll_avalon_post_edit
Info: set_instance_parameter_value pll HIDDEN_IF_PORTS IF#phasecounterselect {input 3} IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#phaseupdown {input 0} IF#scandone {output 0} IF#readdata {output 32} IF#write {input 0} IF#scanclk {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#c2 {output 0} IF#address {input 2} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0} IF#scanclkena {input 0} IF#scandataout {output 0} IF#configupdate {input 0} IF#phasestep {input 0} IF#scandata {input 0}
Info: set_instance_parameter_value pll HIDDEN_IS_FIRST_EDIT 0
Info: set_instance_parameter_value pll HIDDEN_IS_NUMERIC IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK1_MULTIPLY_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1
Info: set_instance_parameter_value pll HIDDEN_MF_PORTS MF#clk 1 MF#inclk 1
Info: set_instance_parameter_value pll HIDDEN_PRIVATES PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 83333.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT1 ps PT#LVDS_PHASE_SHIFT_UNIT0 ps PT#OUTPUT_FREQ_MODE1 0 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 0 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO ps PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ1 50.00000000 PT#OUTPUT_FREQ0 50.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 0 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT1 -5000.00000000 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 6 PT#DIV_FACTOR0 6 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE1 50.000198 PT#EFF_OUTPUT_FREQ_VALUE0 50.000198 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK4 0 PT#STICKY_CLK3 0 PT#STICKY_CLK2 0 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK1 0 PT#MIRROR_CLK0 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#CLKLOSS_CHECK 0 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#PHASE_SHIFT_UNIT1 ps PT#PHASE_SHIFT_UNIT0 ps PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR1 25 PT#MULT_FACTOR0 25 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1552906147954125.mif PT#ACTIVECLK_CHECK 0
Info: set_instance_parameter_value pll HIDDEN_USED_PORTS UP#c1 used UP#c0 used UP#inclk0 used
Info: set_instance_parameter_value pll INCLK0_INPUT_FREQUENCY 83333
Info: set_instance_parameter_value pll INCLK1_INPUT_FREQUENCY
Info: set_instance_parameter_value pll INTENDED_DEVICE_FAMILY MAX 10
Info: set_instance_parameter_value pll INVALID_LOCK_MULTIPLIER
Info: set_instance_parameter_value pll LOCK_HIGH
Info: set_instance_parameter_value pll LOCK_LOW
Info: set_instance_parameter_value pll OPERATION_MODE NORMAL
Info: set_instance_parameter_value pll PLL_TYPE AUTO
Info: set_instance_parameter_value pll PORT_ACTIVECLOCK PORT_UNUSED
Info: set_instance_parameter_value pll PORT_ARESET PORT_UNUSED
Info: set_instance_parameter_value pll PORT_CLKBAD0 PORT_UNUSED
Info: set_instance_parameter_value pll PORT_CLKBAD1 PORT_UNUSED
Info: set_instance_parameter_value pll PORT_CLKLOSS PORT_UNUSED
Info: set_instance_parameter_value pll PORT_CLKSWITCH PORT_UNUSED
Info: set_instance_parameter_value pll PORT_CONFIGUPDATE PORT_UNUSED
Info: set_instance_parameter_value pll PORT_ENABLE0
Info: set_instance_parameter_value pll PORT_ENABLE1
Info: set_instance_parameter_value pll PORT_FBIN PORT_UNUSED
Info: set_instance_parameter_value pll PORT_FBOUT
Info: set_instance_parameter_value pll PORT_INCLK0 PORT_USED
Info: set_instance_parameter_value pll PORT_INCLK1 PORT_UNUSED
Info: set_instance_parameter_value pll PORT_LOCKED PORT_UNUSED
Info: set_instance_parameter_value pll PORT_PFDENA PORT_UNUSED
Info: set_instance_parameter_value pll PORT_PHASECOUNTERSELECT PORT_UNUSED
Info: set_instance_parameter_value pll PORT_PHASEDONE PORT_UNUSED
Info: set_instance_parameter_value pll PORT_PHASESTEP PORT_UNUSED
Info: set_instance_parameter_value pll PORT_PHASEUPDOWN PORT_UNUSED
Info: set_instance_parameter_value pll PORT_PLLENA PORT_UNUSED
Info: set_instance_parameter_value pll PORT_SCANACLR PORT_UNUSED
Info: set_instance_parameter_value pll PORT_SCANCLK PORT_UNUSED
Info: set_instance_parameter_value pll PORT_SCANCLKENA PORT_UNUSED
Info: set_instance_parameter_value pll PORT_SCANDATA PORT_UNUSED
Info: set_instance_parameter_value pll PORT_SCANDATAOUT PORT_UNUSED
Info: set_instance_parameter_value pll PORT_SCANDONE PORT_UNUSED
Info: set_instance_parameter_value pll PORT_SCANREAD PORT_UNUSED
Info: set_instance_parameter_value pll PORT_SCANWRITE PORT_UNUSED
Info: set_instance_parameter_value pll PORT_SCLKOUT0
Info: set_instance_parameter_value pll PORT_SCLKOUT1
Info: set_instance_parameter_value pll PORT_VCOOVERRANGE
Info: set_instance_parameter_value pll PORT_VCOUNDERRANGE
Info: set_instance_parameter_value pll PORT_clk0 PORT_USED
Info: set_instance_parameter_value pll PORT_clk1 PORT_USED
Info: set_instance_parameter_value pll PORT_clk2 PORT_UNUSED
Info: set_instance_parameter_value pll PORT_clk3 PORT_UNUSED
Info: set_instance_parameter_value pll PORT_clk4 PORT_UNUSED
Info: set_instance_parameter_value pll PORT_clk5 PORT_UNUSED
Info: set_instance_parameter_value pll PORT_clk6
Info: set_instance_parameter_value pll PORT_clk7
Info: set_instance_parameter_value pll PORT_clk8
Info: set_instance_parameter_value pll PORT_clk9
Info: set_instance_parameter_value pll PORT_clkena0 PORT_UNUSED
Info: set_instance_parameter_value pll PORT_clkena1 PORT_UNUSED
Info: set_instance_parameter_value pll PORT_clkena2 PORT_UNUSED
Info: set_instance_parameter_value pll PORT_clkena3 PORT_UNUSED
Info: set_instance_parameter_value pll PORT_clkena4 PORT_UNUSED
Info: set_instance_parameter_value pll PORT_clkena5 PORT_UNUSED
Info: set_instance_parameter_value pll PORT_extclk0 PORT_UNUSED
Info: set_instance_parameter_value pll PORT_extclk1 PORT_UNUSED
Info: set_instance_parameter_value pll PORT_extclk2 PORT_UNUSED
Info: set_instance_parameter_value pll PORT_extclk3 PORT_UNUSED
Info: set_instance_parameter_value pll PORT_extclkena0
Info: set_instance_parameter_value pll PORT_extclkena1
Info: set_instance_parameter_value pll PORT_extclkena2
Info: set_instance_parameter_value pll PORT_extclkena3
Info: set_instance_parameter_value pll PRIMARY_CLOCK
Info: set_instance_parameter_value pll QUALIFY_CONF_DONE
Info: set_instance_parameter_value pll SCAN_CHAIN
Info: set_instance_parameter_value pll SCAN_CHAIN_MIF_FILE
Info: set_instance_parameter_value pll SCLKOUT0_PHASE_SHIFT
Info: set_instance_parameter_value pll SCLKOUT1_PHASE_SHIFT
Info: set_instance_parameter_value pll SELF_RESET_ON_GATED_LOSS_LOCK
Info: set_instance_parameter_value pll SELF_RESET_ON_LOSS_LOCK
Info: set_instance_parameter_value pll SKIP_VCO
Info: set_instance_parameter_value pll SPREAD_FREQUENCY
Info: set_instance_parameter_value pll SWITCH_OVER_COUNTER
Info: set_instance_parameter_value pll SWITCH_OVER_ON_GATED_LOCK
Info: set_instance_parameter_value pll SWITCH_OVER_ON_LOSSCLK
Info: set_instance_parameter_value pll SWITCH_OVER_TYPE
Info: set_instance_parameter_value pll USING_FBMIMICBIDIR_PORT
Info: set_instance_parameter_value pll VALID_LOCK_MULTIPLIER
Info: set_instance_parameter_value pll VCO_DIVIDE_BY
Info: set_instance_parameter_value pll VCO_FREQUENCY_CONTROL
Info: set_instance_parameter_value pll VCO_MULTIPLY_BY
Info: set_instance_parameter_value pll VCO_PHASE_SHIFT_STEP
Info: set_instance_parameter_value pll WIDTH_CLOCK 5
Info: set_instance_parameter_value pll WIDTH_PHASECOUNTERSELECT
Info: add_instance sdram_controller altera_avalon_new_sdram_controller 19.1
Info: apply_preset sdram_controller TEI0001_single_W9864G6JT-6
Info: add_instance spi_flash altera_avalon_spi 19.1
Info: set_instance_parameter_value spi_flash clockPhase 0
Info: set_instance_parameter_value spi_flash clockPolarity 0
Info: set_instance_parameter_value spi_flash dataWidth 8
Info: set_instance_parameter_value spi_flash disableAvalonFlowControl 0
Info: set_instance_parameter_value spi_flash insertDelayBetweenSlaveSelectAndSClk 0
Info: set_instance_parameter_value spi_flash insertSync 0
Info: set_instance_parameter_value spi_flash lsbOrderedFirst 0
Info: set_instance_parameter_value spi_flash masterSPI 1
Info: set_instance_parameter_value spi_flash numberOfSlaves 1
Info: set_instance_parameter_value spi_flash syncRegDepth 2
Info: set_instance_parameter_value spi_flash targetClockRate 128000.0
Info: set_instance_parameter_value spi_flash targetSlaveSelectToSClkDelay 0.0
Info: add_instance spi_g_sensor altera_avalon_spi 19.1
Info: set_instance_parameter_value spi_g_sensor clockPhase 0
Info: set_instance_parameter_value spi_g_sensor clockPolarity 0
Info: set_instance_parameter_value spi_g_sensor dataWidth 8
Info: set_instance_parameter_value spi_g_sensor disableAvalonFlowControl 0
Info: set_instance_parameter_value spi_g_sensor insertDelayBetweenSlaveSelectAndSClk 0
Info: set_instance_parameter_value spi_g_sensor insertSync 0
Info: set_instance_parameter_value spi_g_sensor lsbOrderedFirst 0
Info: set_instance_parameter_value spi_g_sensor masterSPI 1
Info: set_instance_parameter_value spi_g_sensor numberOfSlaves 1
Info: set_instance_parameter_value spi_g_sensor syncRegDepth 2
Info: set_instance_parameter_value spi_g_sensor targetClockRate 128000.0
Info: set_instance_parameter_value spi_g_sensor targetSlaveSelectToSClkDelay 0.0
Info: add_instance sysid altera_avalon_sysid_qsys 19.1
Info: set_instance_parameter_value sysid id 403892959
Info: add_instance uart altera_avalon_uart 19.1
Info: set_instance_parameter_value uart baud 115200
Info: set_instance_parameter_value uart dataBits 8
Info: set_instance_parameter_value uart fixedBaud 1
Info: set_instance_parameter_value uart parity NONE
Info: set_instance_parameter_value uart simCharStream
Info: set_instance_parameter_value uart simInteractiveInputEnable 0
Info: set_instance_parameter_value uart simInteractiveOutputEnable 0
Info: set_instance_parameter_value uart simTrueBaud 0
Info: set_instance_parameter_value uart stopBits 1
Info: set_instance_parameter_value uart syncRegDepth 2
Info: set_instance_parameter_value uart useCtsRts 0
Info: set_instance_parameter_value uart useEopRegister 0
Info: set_instance_parameter_value uart useRelativePathForSimFile 0
Info: add_interface clk_in clock sink
Info: set_interface_property clk_in EXPORT_OF clk.clk_in
Info: add_interface pio_led conduit end
Info: set_interface_property pio_led EXPORT_OF pio_led.external_connection
Info: add_interface pio_mode conduit end
Info: set_interface_property pio_mode EXPORT_OF pio_mode.external_connection
Info: add_interface reset reset sink
Info: set_interface_property reset EXPORT_OF clk.clk_in_reset
Info: add_interface sdram conduit end
Info: set_interface_property sdram EXPORT_OF sdram_controller.wire
Info: add_interface sdram_clk clock source
Info: set_interface_property sdram_clk EXPORT_OF pll.c1
Info: add_interface spi_flash conduit end
Info: set_interface_property spi_flash EXPORT_OF spi_flash.external
Info: add_interface spi_g_sen conduit end
Info: set_interface_property spi_g_sen EXPORT_OF spi_g_sensor.external
Info: add_interface uart conduit end
Info: set_interface_property uart EXPORT_OF uart.external_connection
Info: add_connection clk.clk pll.inclk_interface
Info: add_connection clk.clk_reset nios2.reset
Info: add_connection clk.clk_reset onchip_flash.nreset
Info: add_connection clk.clk_reset pio_led.reset
Info: add_connection clk.clk_reset pio_mode.reset
Info: add_connection clk.clk_reset pll.inclk_interface_reset
Info: add_connection clk.clk_reset sdram_controller.reset
Info: add_connection clk.clk_reset spi_flash.reset
Info: add_connection clk.clk_reset spi_g_sensor.reset
Info: add_connection clk.clk_reset sysid.reset
Info: add_connection clk.clk_reset uart.reset
Info: add_connection nios2.data_master nios2.debug_mem_slave
Info: set_connection_parameter_value nios2.data_master/nios2.debug_mem_slave arbitrationPriority 1
Info: set_connection_parameter_value nios2.data_master/nios2.debug_mem_slave baseAddress 0x01100800
Info: set_connection_parameter_value nios2.data_master/nios2.debug_mem_slave defaultConnection 0
Info: add_connection nios2.data_master onchip_flash.csr
Info: set_connection_parameter_value nios2.data_master/onchip_flash.csr arbitrationPriority 1
Info: set_connection_parameter_value nios2.data_master/onchip_flash.csr baseAddress 0x01101130
Info: set_connection_parameter_value nios2.data_master/onchip_flash.csr defaultConnection 0
Info: add_connection nios2.data_master onchip_flash.data
Info: set_connection_parameter_value nios2.data_master/onchip_flash.data arbitrationPriority 1
Info: set_connection_parameter_value nios2.data_master/onchip_flash.data baseAddress 0x01080000
Info: set_connection_parameter_value nios2.data_master/onchip_flash.data defaultConnection 0
Info: add_connection nios2.data_master pio_led.s1
Info: set_connection_parameter_value nios2.data_master/pio_led.s1 arbitrationPriority 1
Info: set_connection_parameter_value nios2.data_master/pio_led.s1 baseAddress 0x01101110
Info: set_connection_parameter_value nios2.data_master/pio_led.s1 defaultConnection 0
Info: add_connection nios2.data_master pio_mode.s1
Info: set_connection_parameter_value nios2.data_master/pio_mode.s1 arbitrationPriority 1
Info: set_connection_parameter_value nios2.data_master/pio_mode.s1 baseAddress 0x01101100
Info: set_connection_parameter_value nios2.data_master/pio_mode.s1 defaultConnection 0
Info: add_connection nios2.data_master pll.pll_slave
Info: set_connection_parameter_value nios2.data_master/pll.pll_slave arbitrationPriority 1
Info: set_connection_parameter_value nios2.data_master/pll.pll_slave baseAddress 0x011010f0
Info: set_connection_parameter_value nios2.data_master/pll.pll_slave defaultConnection 0
Info: add_connection nios2.data_master sdram_controller.s1
Info: set_connection_parameter_value nios2.data_master/sdram_controller.s1 arbitrationPriority 1
Info: set_connection_parameter_value nios2.data_master/sdram_controller.s1 baseAddress 0x00800000
Info: set_connection_parameter_value nios2.data_master/sdram_controller.s1 defaultConnection 0
Info: add_connection nios2.data_master spi_flash.spi_control_port
Info: set_connection_parameter_value nios2.data_master/spi_flash.spi_control_port arbitrationPriority 1
Info: set_connection_parameter_value nios2.data_master/spi_flash.spi_control_port baseAddress 0x011010a0
Info: set_connection_parameter_value nios2.data_master/spi_flash.spi_control_port defaultConnection 0
Info: add_connection nios2.data_master spi_g_sensor.spi_control_port
Info: set_connection_parameter_value nios2.data_master/spi_g_sensor.spi_control_port arbitrationPriority 1
Info: set_connection_parameter_value nios2.data_master/spi_g_sensor.spi_control_port baseAddress 0x01101080
Info: set_connection_parameter_value nios2.data_master/spi_g_sensor.spi_control_port defaultConnection 0
Info: add_connection nios2.data_master sysid.control_slave
Info: set_connection_parameter_value nios2.data_master/sysid.control_slave arbitrationPriority 1
Info: set_connection_parameter_value nios2.data_master/sysid.control_slave baseAddress 0x01101128
Info: set_connection_parameter_value nios2.data_master/sysid.control_slave defaultConnection 0
Info: add_connection nios2.data_master uart.s1
Info: set_connection_parameter_value nios2.data_master/uart.s1 arbitrationPriority 1
Info: set_connection_parameter_value nios2.data_master/uart.s1 baseAddress 0x01101060
Info: set_connection_parameter_value nios2.data_master/uart.s1 defaultConnection 0
Info: add_connection nios2.debug_reset_request nios2.reset
Info: add_connection nios2.debug_reset_request onchip_flash.nreset
Info: add_connection nios2.debug_reset_request pio_led.reset
Info: add_connection nios2.debug_reset_request pio_mode.reset
Info: add_connection nios2.debug_reset_request pll.inclk_interface_reset
Info: add_connection nios2.debug_reset_request sdram_controller.reset
Info: add_connection nios2.debug_reset_request spi_flash.reset
Info: add_connection nios2.debug_reset_request spi_g_sensor.reset
Info: add_connection nios2.debug_reset_request sysid.reset
Info: add_connection nios2.debug_reset_request uart.reset
Info: add_connection nios2.instruction_master nios2.debug_mem_slave
Info: set_connection_parameter_value nios2.instruction_master/nios2.debug_mem_slave arbitrationPriority 1
Info: set_connection_parameter_value nios2.instruction_master/nios2.debug_mem_slave baseAddress 0x01100800
Info: set_connection_parameter_value nios2.instruction_master/nios2.debug_mem_slave defaultConnection 0
Info: add_connection nios2.instruction_master onchip_flash.data
Info: set_connection_parameter_value nios2.instruction_master/onchip_flash.data arbitrationPriority 1
Info: set_connection_parameter_value nios2.instruction_master/onchip_flash.data baseAddress 0x01080000
Info: set_connection_parameter_value nios2.instruction_master/onchip_flash.data defaultConnection 0
Info: add_connection nios2.instruction_master pio_led.s1
Info: set_connection_parameter_value nios2.instruction_master/pio_led.s1 arbitrationPriority 1
Info: set_connection_parameter_value nios2.instruction_master/pio_led.s1 baseAddress 0x01101110
Info: set_connection_parameter_value nios2.instruction_master/pio_led.s1 defaultConnection 0
Info: add_connection nios2.instruction_master pio_mode.s1
Info: set_connection_parameter_value nios2.instruction_master/pio_mode.s1 arbitrationPriority 1
Info: set_connection_parameter_value nios2.instruction_master/pio_mode.s1 baseAddress 0x01101100
Info: set_connection_parameter_value nios2.instruction_master/pio_mode.s1 defaultConnection 0
Info: add_connection nios2.instruction_master pll.pll_slave
Info: set_connection_parameter_value nios2.instruction_master/pll.pll_slave arbitrationPriority 1
Info: set_connection_parameter_value nios2.instruction_master/pll.pll_slave baseAddress 0x011010f0
Info: set_connection_parameter_value nios2.instruction_master/pll.pll_slave defaultConnection 0
Info: add_connection nios2.instruction_master sdram_controller.s1
Info: set_connection_parameter_value nios2.instruction_master/sdram_controller.s1 arbitrationPriority 1
Info: set_connection_parameter_value nios2.instruction_master/sdram_controller.s1 baseAddress 0x00800000
Info: set_connection_parameter_value nios2.instruction_master/sdram_controller.s1 defaultConnection 0
Info: add_connection nios2.instruction_master spi_flash.spi_control_port
Info: set_connection_parameter_value nios2.instruction_master/spi_flash.spi_control_port arbitrationPriority 1
Info: set_connection_parameter_value nios2.instruction_master/spi_flash.spi_control_port baseAddress 0x011010a0
Info: set_connection_parameter_value nios2.instruction_master/spi_flash.spi_control_port defaultConnection 0
Info: add_connection nios2.instruction_master spi_g_sensor.spi_control_port
Info: set_connection_parameter_value nios2.instruction_master/spi_g_sensor.spi_control_port arbitrationPriority 1
Info: set_connection_parameter_value nios2.instruction_master/spi_g_sensor.spi_control_port baseAddress 0x01101080
Info: set_connection_parameter_value nios2.instruction_master/spi_g_sensor.spi_control_port defaultConnection 0
Info: add_connection nios2.instruction_master sysid.control_slave
Info: set_connection_parameter_value nios2.instruction_master/sysid.control_slave arbitrationPriority 1
Info: set_connection_parameter_value nios2.instruction_master/sysid.control_slave baseAddress 0x01101128
Info: set_connection_parameter_value nios2.instruction_master/sysid.control_slave defaultConnection 0
Info: add_connection nios2.instruction_master uart.s1
Info: set_connection_parameter_value nios2.instruction_master/uart.s1 arbitrationPriority 1
Info: set_connection_parameter_value nios2.instruction_master/uart.s1 baseAddress 0x01101060
Info: set_connection_parameter_value nios2.instruction_master/uart.s1 defaultConnection 0
Info: add_connection nios2.irq spi_flash.irq
Info: set_connection_parameter_value nios2.irq/spi_flash.irq irqNumber 1
Info: add_connection nios2.irq spi_g_sensor.irq
Info: set_connection_parameter_value nios2.irq/spi_g_sensor.irq irqNumber 2
Info: add_connection nios2.irq uart.irq
Info: set_connection_parameter_value nios2.irq/uart.irq irqNumber 0
Info: add_connection pll.c0 nios2.clk
Info: add_connection pll.c0 onchip_flash.clk
Info: add_connection pll.c0 pio_led.clk
Info: add_connection pll.c0 pio_mode.clk
Info: add_connection pll.c0 sdram_controller.clk
Info: add_connection pll.c0 spi_flash.clk
Info: add_connection pll.c0 spi_g_sensor.clk
Info: add_connection pll.c0 sysid.clk
Info: add_connection pll.c0 uart.clk
Info: set_interconnect_requirement $system qsys_mm.clockCrossingAdapter HANDSHAKE
Info: set_interconnect_requirement $system qsys_mm.enableEccProtection FALSE
Info: set_interconnect_requirement $system qsys_mm.insertDefaultSlave FALSE
Info: set_interconnect_requirement $system qsys_mm.maxAdditionalLatency 1
Info: auto_assign_system_base_addresses
Info: save_system NIOS_test_board.qsys
Info: [TE_QUART-03] Create qsys -> done
------------------------------
Info: [TE_QUART-04] Generate qsys. It can take a few minutes, please wait ...
Info: [TE_QUART-05] Command results on: exec c:/intelfpga_lite/19.1/quartus/sopc_builder/bin/qsys-generate.exe C:/data/Manufucture/Quartus/19.1/test_board/quartus/NIOS_test_board.qsys --synthesis=vhdl -bsf {--search-path=C:/data/Manufucture/Quartus/19.1/test_board/quartus/**/*,C:/data/Manufucture/Quartus/19.1/test_board/settings/*,$}:
Info: Saving generation log to C:/data/Manufucture/Quartus/19.1/test_board/quartus/NIOS_test_board/NIOS_test_board_generation.rpt
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate C:\data\Manufucture\Quartus\19.1\test_board\quartus\NIOS_test_board.qsys --block-symbol-file --output-directory=C:\data\Manufucture\Quartus\19.1\test_board\quartus\NIOS_test_board --family="MAX 10" --part=10M08SAU169C8G
Info: Loading quartus/NIOS_test_board.qsys
Info: Reading input file
Info: Adding clk [clock_source 19.1]
Info: Parameterizing module clk
Info: Adding nios2 [altera_nios2_gen2 19.1]
Info: Parameterizing module nios2
Info: Adding onchip_flash [altera_onchip_flash 19.1]
Info: Parameterizing module onchip_flash
Info: Adding pio_led [altera_avalon_pio 19.1]
Info: Parameterizing module pio_led
Info: Adding pio_mode [altera_avalon_pio 19.1]
Info: Parameterizing module pio_mode
Info: Adding pll [altpll 19.1]
Info: Parameterizing module pll
Info: Adding sdram_controller [altera_avalon_new_sdram_controller 19.1]
Info: Parameterizing module sdram_controller
Info: Adding spi_flash [altera_avalon_spi 19.1]
Info: Parameterizing module spi_flash
Info: Adding spi_g_sensor [altera_avalon_spi 19.1]
Info: Parameterizing module spi_g_sensor
Info: Adding sysid [altera_avalon_sysid_qsys 19.1]
Info: Parameterizing module sysid
Info: Adding uart [altera_avalon_uart 19.1]
Info: Parameterizing module uart
Info: Building connections
Info: Parameterizing connections
Info: Validating
Info: Done reading input file
Info: NIOS_test_board.pio_mode: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: NIOS_test_board.sdram_controller: SDRAM Controller will only be supported in Quartus Prime Standard Edition in the future release.
Info: NIOS_test_board.sysid: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
Info: NIOS_test_board.sysid: Time stamp will be automatically updated when this component is generated.
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info:
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate C:\data\Manufucture\Quartus\19.1\test_board\quartus\NIOS_test_board.qsys --synthesis=VHDL --output-directory=C:\data\Manufucture\Quartus\19.1\test_board\quartus\NIOS_test_board\synthesis --family="MAX 10" --part=10M08SAU169C8G
Info: Loading quartus/NIOS_test_board.qsys
Info: Reading input file
Info: Adding clk [clock_source 19.1]
Info: Parameterizing module clk
Info: Adding nios2 [altera_nios2_gen2 19.1]
Info: Parameterizing module nios2
Info: Adding onchip_flash [altera_onchip_flash 19.1]
Info: Parameterizing module onchip_flash
Info: Adding pio_led [altera_avalon_pio 19.1]
Info: Parameterizing module pio_led
Info: Adding pio_mode [altera_avalon_pio 19.1]
Info: Parameterizing module pio_mode
Info: Adding pll [altpll 19.1]
Info: Parameterizing module pll
Info: Adding sdram_controller [altera_avalon_new_sdram_controller 19.1]
Info: Parameterizing module sdram_controller
Info: Adding spi_flash [altera_avalon_spi 19.1]
Info: Parameterizing module spi_flash
Info: Adding spi_g_sensor [altera_avalon_spi 19.1]
Info: Parameterizing module spi_g_sensor
Info: Adding sysid [altera_avalon_sysid_qsys 19.1]
Info: Parameterizing module sysid
Info: Adding uart [altera_avalon_uart 19.1]
Info: Parameterizing module uart
Info: Building connections
Info: Parameterizing connections
Info: Validating
Info: Done reading input file
Info: NIOS_test_board.pio_mode: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: NIOS_test_board.sdram_controller: SDRAM Controller will only be supported in Quartus Prime Standard Edition in the future release.
Info: NIOS_test_board.sysid: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
Info: NIOS_test_board.sysid: Time stamp will be automatically updated when this component is generated.
Info: NIOS_test_board: Generating NIOS_test_board "NIOS_test_board" for QUARTUS_SYNTH
Info: Inserting clock-crossing logic between cmd_demux.src4 and cmd_mux_004.sink0
Info: Inserting clock-crossing logic between cmd_demux_001.src3 and cmd_mux_004.sink1
Info: Inserting clock-crossing logic between rsp_demux_004.src0 and rsp_mux.sink4
Info: Inserting clock-crossing logic between rsp_demux_004.src1 and rsp_mux_001.sink3
Info: nios2: "NIOS_test_board" instantiated altera_nios2_gen2 "nios2"
Info: onchip_flash: Generating top-level entity altera_onchip_flash
Info: onchip_flash: "NIOS_test_board" instantiated altera_onchip_flash "onchip_flash"
Info: pio_led: Starting RTL generation for module 'NIOS_test_board_pio_led'
Info: pio_led: Generation command is [exec C:/intelfpga_lite/19.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/19.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/19.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=NIOS_test_board_pio_led --dir=C:/Users/norin/AppData/Local/Temp/alt8492_5218307135474003278.dir/0003_pio_led_gen/ --quartus_dir=C:/intelfpga_lite/19.1/quartus --verilog --config=C:/Users/norin/AppData/Local/Temp/alt8492_5218307135474003278.dir/0003_pio_led_gen//NIOS_test_board_pio_led_component_configuration.pl --do_build_sim=0 ]
Info: pio_led: Done RTL generation for module 'NIOS_test_board_pio_led'
Info: pio_led: "NIOS_test_board" instantiated altera_avalon_pio "pio_led"
Info: pio_mode: Starting RTL generation for module 'NIOS_test_board_pio_mode'
Info: pio_mode: Generation command is [exec C:/intelfpga_lite/19.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/19.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/19.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=NIOS_test_board_pio_mode --dir=C:/Users/norin/AppData/Local/Temp/alt8492_5218307135474003278.dir/0004_pio_mode_gen/ --quartus_dir=C:/intelfpga_lite/19.1/quartus --verilog --config=C:/Users/norin/AppData/Local/Temp/alt8492_5218307135474003278.dir/0004_pio_mode_gen//NIOS_test_board_pio_mode_component_configuration.pl --do_build_sim=0 ]
Info: pio_mode: Done RTL generation for module 'NIOS_test_board_pio_mode'
Info: pio_mode: "NIOS_test_board" instantiated altera_avalon_pio "pio_mode"
Info: pll: "NIOS_test_board" instantiated altpll "pll"
Info: sdram_controller: Starting RTL generation for module 'NIOS_test_board_sdram_controller'
Info: sdram_controller: Generation command is [exec C:/intelfpga_lite/19.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/19.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/19.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_new_sdram_controller -- C:/intelfpga_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_new_sdram_controller/generate_rtl.pl --name=NIOS_test_board_sdram_controller --dir=C:/Users/norin/AppData/Local/Temp/alt8492_5218307135474003278.dir/0007_sdram_controller_gen/ --quartus_dir=C:/intelfpga_lite/19.1/quartus --verilog --config=C:/Users/norin/AppData/Local/Temp/alt8492_5218307135474003278.dir/0007_sdram_controller_gen//NIOS_test_board_sdram_controller_component_configuration.pl --do_build_sim=0 ]
Info: sdram_controller: Done RTL generation for module 'NIOS_test_board_sdram_controller'
Info: sdram_controller: "NIOS_test_board" instantiated altera_avalon_new_sdram_controller "sdram_controller"
Info: spi_flash: Starting RTL generation for module 'NIOS_test_board_spi_flash'
Info: spi_flash: Generation command is [exec C:/intelfpga_lite/19.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/19.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/19.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_spi -- C:/intelfpga_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_spi/generate_rtl.pl --name=NIOS_test_board_spi_flash --dir=C:/Users/norin/AppData/Local/Temp/alt8492_5218307135474003278.dir/0008_spi_flash_gen/ --quartus_dir=C:/intelfpga_lite/19.1/quartus --verilog --config=C:/Users/norin/AppData/Local/Temp/alt8492_5218307135474003278.dir/0008_spi_flash_gen//NIOS_test_board_spi_flash_component_configuration.pl --do_build_sim=0 ]
Info: spi_flash: Done RTL generation for module 'NIOS_test_board_spi_flash'
Info: spi_flash: "NIOS_test_board" instantiated altera_avalon_spi "spi_flash"
Info: sysid: "NIOS_test_board" instantiated altera_avalon_sysid_qsys "sysid"
Info: uart: Starting RTL generation for module 'NIOS_test_board_uart'
Info: uart: Generation command is [exec C:/intelfpga_lite/19.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/19.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/19.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_uart -- C:/intelfpga_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_uart/generate_rtl.pl --name=NIOS_test_board_uart --dir=C:/Users/norin/AppData/Local/Temp/alt8492_5218307135474003278.dir/0010_uart_gen/ --quartus_dir=C:/intelfpga_lite/19.1/quartus --verilog --config=C:/Users/norin/AppData/Local/Temp/alt8492_5218307135474003278.dir/0010_uart_gen//NIOS_test_board_uart_component_configuration.pl --do_build_sim=0 ]
Info: uart: Done RTL generation for module 'NIOS_test_board_uart'
Info: uart: "NIOS_test_board" instantiated altera_avalon_uart "uart"
Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_007: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_008: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_009: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_010: Inserting error_adapter: error_adapter_0
Info: mm_interconnect_0: "NIOS_test_board" instantiated altera_mm_interconnect "mm_interconnect_0"
Info: irq_mapper: "NIOS_test_board" instantiated altera_irq_mapper "irq_mapper"
Info: rst_controller: "NIOS_test_board" instantiated altera_reset_controller "rst_controller"
Info: cpu: Starting RTL generation for module 'NIOS_test_board_nios2_cpu'
Info: cpu: Generation command is [exec C:/intelFPGA_lite/19.1/quartus/bin64//perl/bin/perl.exe -I C:/intelfpga_lite/19.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/19.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/intelfpga_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/intelfpga_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/intelfpga_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/intelfpga_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.pl --name=NIOS_test_board_nios2_cpu --dir=C:/Users/norin/AppData/Local/Temp/alt8492_5218307135474003278.dir/0013_cpu_gen/ --quartus_bindir=C:/intelFPGA_lite/19.1/quartus/bin64/ --verilog --config=C:/Users/norin/AppData/Local/Temp/alt8492_5218307135474003278.dir/0013_cpu_gen//NIOS_test_board_nios2_cpu_processor_configuration.pl --do_build_sim=0 ]
Info: cpu: # 2020.08.18 10:04:43 (*) Starting Nios II generation
Info: cpu: # 2020.08.18 10:04:43 (*) Elaborating CPU configuration settings
Info: cpu: # 2020.08.18 10:04:43 (*) Creating all objects for CPU
Info: cpu: # 2020.08.18 10:04:44 (*) Generating RTL from CPU objects
Info: cpu: # 2020.08.18 10:04:44 (*) Creating plain-text RTL
Info: cpu: # 2020.08.18 10:04:45 (*) Done Nios II generation
Info: cpu: Done RTL generation for module 'NIOS_test_board_nios2_cpu'
Info: cpu: "nios2" instantiated altera_nios2_gen2_unit "cpu"
Info: nios2_data_master_translator: "mm_interconnect_0" instantiated altera_merlin_master_translator "nios2_data_master_translator"
Info: sysid_control_slave_translator: "mm_interconnect_0" instantiated altera_merlin_slave_translator "sysid_control_slave_translator"
Info: nios2_data_master_agent: "mm_interconnect_0" instantiated altera_merlin_master_agent "nios2_data_master_agent"
Info: sysid_control_slave_agent: "mm_interconnect_0" instantiated altera_merlin_slave_agent "sysid_control_slave_agent"
Info: sysid_control_slave_agent_rsp_fifo: "mm_interconnect_0" instantiated altera_avalon_sc_fifo "sysid_control_slave_agent_rsp_fifo"
Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router"
Info: router_001: "mm_interconnect_0" instantiated altera_merlin_router "router_001"
Info: router_002: "mm_interconnect_0" instantiated altera_merlin_router "router_002"
Info: router_003: "mm_interconnect_0" instantiated altera_merlin_router "router_003"
Info: router_009: "mm_interconnect_0" instantiated altera_merlin_router "router_009"
Info: sdram_controller_s1_burst_adapter: "mm_interconnect_0" instantiated altera_merlin_burst_adapter "sdram_controller_s1_burst_adapter"
Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"
Info: cmd_demux_001: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux_001"
Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"
Info: cmd_mux_001: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux_001"
Info: Reusing file C:/data/Manufucture/Quartus/19.1/test_board/quartus/NIOS_test_board/synthesis/submodules/altera_merlin_arbitrator.sv
Info: rsp_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux"
Info: rsp_demux_001: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux_001"
Info: rsp_demux_004: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux_004"
Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"
Info: Reusing file C:/data/Manufucture/Quartus/19.1/test_board/quartus/NIOS_test_board/synthesis/submodules/altera_merlin_arbitrator.sv
Info: rsp_mux_001: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux_001"
Info: Reusing file C:/data/Manufucture/Quartus/19.1/test_board/quartus/NIOS_test_board/synthesis/submodules/altera_merlin_arbitrator.sv
Info: sdram_controller_s1_rsp_width_adapter: "mm_interconnect_0" instantiated altera_merlin_width_adapter "sdram_controller_s1_rsp_width_adapter"
Info: Reusing file C:/data/Manufucture/Quartus/19.1/test_board/quartus/NIOS_test_board/synthesis/submodules/altera_merlin_address_alignment.sv
Info: Reusing file C:/data/Manufucture/Quartus/19.1/test_board/quartus/NIOS_test_board/synthesis/submodules/altera_merlin_burst_uncompressor.sv
Info: crosser: "mm_interconnect_0" instantiated altera_avalon_st_handshake_clock_crosser "crosser"
Info: Reusing file C:/data/Manufucture/Quartus/19.1/test_board/quartus/NIOS_test_board/synthesis/submodules/altera_avalon_st_pipeline_base.v
Info: avalon_st_adapter: "mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"
Info: avalon_st_adapter_007: "mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter_007"
Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0"
Info: error_adapter_0: "avalon_st_adapter_007" instantiated error_adapter "error_adapter_0"
Info: NIOS_test_board: Done "NIOS_test_board" with 40 modules, 71 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis
Info: [TE_QUART-06] Generate qsys -> done
------------------------------
-----------------------------------------------------------------------
Info: [TE_DES-37] Create software project. Please wait ...
Info: [TE_SDK-01] Create software files. Please wait ...
Info: [TE_SDK-04] Create software files -> done
------------------------------
Info: [TE_SDK-05] Create bsp. Please wait ...
Info: [TE_SDK-06] Command results on: exec wsl bash /mnt/c/intelfpga_lite/19.1/nios2eds/nios2_command_shell.sh ./create-this-bsp --no-make:
create-this-bsp: Running "nios2-bsp hal . C:/data/Manufucture/Quartus/19.1/test_board/quartus/NIOS_test_board.sopcinfo --set hal.enable_small_c_library true --set hal.enable_c_plus_plus false --set hal.enable_reduced_device_drivers true --set hal.linker.exception_stack_memory_region_name sdram_controller --set hal.linker.interrupt_stack_memory_region_name sdram_controller --cmd update_section_mapping .bss sdram_controller --cmd update_section_mapping .heap sdram_controller --cmd update_section_mapping .rwdata sdram_controller --cmd update_section_mapping .stack sdram_controller --cmd update_section_mapping .rodata sdram_controller --cmd update_section_mapping .text sdram_controller --cpu-name nios2"
nios2-bsp: Using /mnt/c/intelfpga_lite/19.1/nios2eds/sdk2/bin/bsp-set-defaults.tcl to set system-dependent settings.
nios2-bsp: Creating new BSP because ./settings.bsp doesn't exist.
nios2-bsp hal . C:/data/Manufucture/Quartus/19.1/test_board/quartus/NIOS_test_board.sopcinfo --set hal.enable_small_c_library true --set hal.enable_c_plus_plus false --set hal.enable_reduced_device_drivers true --set hal.linker.exception_stack_memory_region_name sdram_controller --set hal.linker.interrupt_stack_memory_region_name sdram_controller --cmd update_section_mapping .bss sdram_controller --cmd update_section_mapping .heap sdram_controller --cmd update_section_mapping .rwdata sdram_controller --cmd update_section_mapping .stack sdram_controller --cmd update_section_mapping .rodata sdram_controller --cmd update_section_mapping .text sdram_controller --cpu-name nios2 failed
nios2-bsp: SOPC design argument C:/data/Manufucture/Quartus/19.1/test_board/quartus/NIOS_test_board.sopcinfo isn't a directory or a file
Info: [TE_SDK-07] Create bsp -> done
------------------------------
Info: [TE_SDK-08] Create app. Please wait ...
Info: [TE_SDK-09] Command results on: exec wsl bash /mnt/c/intelfpga_lite/19.1/nios2eds/nios2_command_shell.sh ./create-this-app --no-make:
create-this-bsp failed
/mnt/c/data/Manufucture/Quartus/19.1/test_board/software/test_board/create-this-app: line 53: pushd: C:/data/Manufucture/Quartus/19.1/test_board/software/test_board_bsp/: No such file or directory
/mnt/c/data/Manufucture/Quartus/19.1/test_board/software/test_board/create-this-app: line 54: ./create-this-bsp: No such file or directory
Info: [TE_SDK-10] Create app -> done
------------------------------
Info: [TE_SDK-23] Modify sdk files. Please wait ...
Error: [TE_DES-64] Script (TE::SDK::modify_sdk_files) failed: couldn't open "C:/data/Manufucture/Quartus/19.1/test_board/software/test_board/Makefile": no such file or directory
Error: [TE_DES-31] Script (TE::DES::run_sw_project) failed:
Error: [TE_TK-11] (TE) Script (TE::DES::run_project) failed: .