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#1

MAX1000 community projects / Re: Playing ZX Spectrum in HDM...

Last post by Subcritical - March 25, 2025, 06:21:35 PM

Having already created two different screensaver implementations, we used a VT52 terminal. If you look at the upper left corner, you'll see the seconds. They are slightly faster since, for better visualization in DVI(HDMI, we set a clock of 50.40 MHz, The design uses at first a 50MHz clock as the initial design frequency.

ATLAS Sources:
https://github.com/AtlasFPGA/vt52

Intel/Altera's intellectual properties, such as the phase-locked loop or "PLL," have been approximated to a pixel clock of 25.2 MHz, which gives a resolution of 640x480 with 60Hz vertical synchronization, the exact clock is 25,175Mhz.

You will typically encounter the following errors if you start from a CYCLONE design in families I through IV.
Typically, projects have this configuration:
Single Uncompressed Image (912Kbits UFM)

Let's view the error:
"16031 Current Internal Configuration mode does not support memory initialization or ROM.
Select Internal Configuration mode with ERAM."

This is a memory initialization error.

Now we apply the address and change the parameters.
Assignments - Device - Device and Pin Options - Configuration - Configuration Mode: Single uncompressed image with Memory Initialization
Translate.

The design compilation has been successful.
It is very important that the "IP" intellectual property rights are transferred to the MAX 10 family, given that we have a Max1000 SuperCPLD/FPGA.

Let's begin programming.
And we'll see how the VT52 terminal design shows the seconds of activity in the upper left corner.

I'm slowly translating the comments into other languages.
Greetings.

#2

MAX1000 community projects / Re: Playing ZX Spectrum in HDM...

Last post by Subcritical - March 25, 2025, 01:35:28 PM

We will rename the signals of the implementation, that uses 24bits of color created by Piotr.go.

Code Select Expand

https://github.com/piotr-go/Lichee-Tang/blob/master/VGA/src/vga.v
To the nomenclature in the previous demo/hdmi demo DVI_1280x1024_max1000.

We visualize the files *.qsf.

VGA.QSF signals:

Code Select Expand

set_location_assignment pin_h6 -to SYS_CLK
set_location_assignment pin_h5 -to TMDS [0]
set_location_assignment pin_k10 -to TMDS [1]
set_location_assignment pin_h13 -to TMDS [2]
set_location_assignment pin_j13 -to TMDS [3]
set_location_assignment pin_k11 -to TMDS [4]
set_location_assignment pin_k12 -to TMDS [5]
set_location_assignment pin_j12 -to TMDS [6]
set_location_assignment pin_l12 -to TMDS [7]

Max10_50.qsf signals:

Code Select Expand

set_location_assignment pin_h6 -to clk12Hz
set_location_assignment pin_h5 -to tmds [0]
set_location_assignment pin_k10 -to tmds [1]
set_location_assignment pin_h13 -to tmds [2]
set_location_assignment pin_j13 -to tmds [3]
set_location_assignment pin_k11 -to tmds [4]
set_location_assignment pin_k12 -to tmds [5]
set_location_assignment pin_j12 -to tmds [6]
set_location_assignment pin_l12 -to tmds [7]

I have made the change of TMDS and SYS_CLK to tmds and CLK12MHz names.

Now change the integrated FPGA.
I proceed to eliminate one by one the assignments of the pins, in pin planner.

I do that because, I want to see the name of the signals.
Let's see if Arrow Blaster is detected.
Appears:

Code Select Expand

USB serial Converter A
USB Serial Converter B

Once the first compilation is finished we enter Pin Planner.
And we see if the name of the signals have been changed.

Next, we will go to all the signs and rename them since we have taken the terminology of the DVI_1280x1024_max1000 screen.
And once the assignments have been changed again, we will proceed to send the flow of data to the Max1000.
And see if the capturer shows the screen_exercise of Piotr.go.

As the signals are seen, they have been renamed, and use the same nomenclature as in the previous screen_exercise.
Once the correspondences of the signals and the pins we rebuilt.

Let's take a walk through the VGA.V file

We will send the data flow to the Max1000.

This exercise is very interesting since it shows how starting from a 640x480 VGA signal with a 60Hz vertical sync.
That makes a 25,175 pixel clock, we visualize the screen at full 24 bits colors, with only 8 HDMI pins.

We will visualize the black box of PPL from intel/altera in the Max 10 family.
We start with a clock from 12MHz.
We approximate by PLL limitations the 25,175MHz Pixel Clock frequency at 25,20000000MHz.
HDMI frequency is 5 times the frequency of pixel clock; that is a 126.00000000MHz Clock.
We visualize that in the Used PLL we could still generate three other frequencies C2, C3. and C4.

#3

UltraScale / Re: TE0820 with TEF1002 and Vi...

Last post by harrx - March 25, 2025, 08:46:11 AM

I think the petalinux boot would not work with any other version, an it would need .xsa file generated from the same Vivado version, i.e. 2019.2

Have you tried a simple PCIe setup, uisng just Vivado and Vitis ?

#4

MAX1000 community projects / Re: Playing ZX Spectrum in HDM...

Last post by Subcritical - March 23, 2025, 03:05:36 PM

With the previous DVI/HDMI pins and the master clock we can create an interesting gradient of color. At a resolution of 1280x1024.

You can translate from this vídeo. I converted the sources from CYC1000 to MAX1000.

The only you need is a HDMI-PMOD, and connect the digital signals with dupont cables.
We need only 8 cables for a DVI/HDMI signal.

I add the sources also for MAX1000.

HDMI-PMOD:


HDMI-SIGNALS:


SCREEN-MAX1000:


SOURCES:
DVI_1280x1024_MAX1000.zip

ORIGINAL SOURCES:
https://github.com/open-design/max10_hdmi/tree/master

#5

UltraScale / Re: TE0820 with TEF1002 and Vi...

Last post by pema - March 20, 2025, 10:47:38 AM

Hi John any news ? 

#6

UltraScale / Re: PCIe conectivity with TEF1...

Last post by harrx - March 18, 2025, 11:12:25 AM

I was able to solve the Flashing issue. vitis now programs the flash memory on TE0820. But, I don't see the Xilinx PCIe Controller with "lspci". I also did a cold reset.

Does anything needs to be configured on the TEf1002 Carrier board for the PCIe to be recognized ?

#7

UltraScale / PCIe conectivity with TEF1002 ...

Last post by harrx - March 18, 2025, 09:48:38 AM

Dear,

I am trying a simple design with a Zynq Ultrascale block (with PCIe enabled) on TE0820. For the PCIe to work, I have connected it withthe TEF1002 Carrier and this sits in one of the PCIe slots on my Desktop Computer.

At this point, I am able to program the device via JTAG, but the flash could not be programmed. Vitis Error: Boot mode for QSPI not supported. I have tried with switches (S3-1:ON, S3-2:OFF; S3-1:ON, S3-2:ON) -- also with dual-parallel qspi selected in Vitis when programming the Flash.

How can I program the flash of TE0820, so to enable the PCIe pin maps ? Is there any alternate way of doing it for a custom project; not building the entire Reference design.

Best regards,
Haris.

#8

UltraScale / TE0820 with TEF1002 and Vivado...

Last post by pema - March 14, 2025, 10:10:15 AM

Hi guys,
I am trying to get the development environment setup for the TE0820-03-03CG-1EA with the carrier Board TEF1002.
However I use Vivado, Vitis and petalinux  2024.2.
Is it possible to convert the reference design to 2024.2 ?

https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0820/Reference_Design/2019.2/TD_TEF1002
Much appreciated !

#9

Trenz Electronic FPGA Modules / Re: Vivado doesn't detect TE0...

Last post by Alex H - March 12, 2025, 08:48:04 PM

Hi Markus,

thanks for your help! I've connected the board to my Windows machine and tried the methods of checking the license. Windows does indeed show only one COM port and the USB View application finds a Digilent USB Device with the serial number starting with 251633..

Therefore I think I can conclude that the license in fact valid?

In Vivado though, the Hardware Server still finds no hardware target. I've tried "auto connect" multiple times.

Greetings
Alex

#10

Trenz Electronic FPGA Modules / Re: Vivado doesn't detect TE0...

Last post by M Kirberg - March 12, 2025, 06:46:56 AM

Hi Alex,

sorry for the late reply... as discussed yesterday in person:


There should be only one serial console when license is correct.


Please see here for methods of identification. (might be best to shortly check this on windows)
https://wiki.trenz-electronic.de/display/PD/TE0790+Identification

If the license is indeed missing (for whatever reason) then you can use this method to fix this yourself:
https://wiki.trenz-electronic.de/display/PD/AMD+FTDI+JTAG+Programmer

I hope that works. If not please contact us via support email and we will have a look at it.

best
markus