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#41
CYC1000 community projects / Re: I present a comunity of IN...
Last post by Subcritical - January 11, 2025, 11:21:51 AMWriting the maximum Command Interpreter Path length , in MSX 1 From Fabio Benabeluto, and Radio-RK86 "РАДИО-86РК".
#42
MAX1000 community projects / Re: Playing ZX Spectrum in HDM...
Last post by Subcritical - January 10, 2025, 07:17:14 PMThis is the lines for using the DVI signal, the max 10 with a 55 nanometer achive the frecuencies of a DVI/Digital_video with no problem.
You can see the pin planner in the photo added.
It is a nice thing to have a 24 or 30 bit color scheme an consumes a very low count kles.
There is a screenshot also of the compiled piotr-go-vga, but consumes only 8 pins.
In order to reproduce a vga signal with 24bits.
You need:
8 Pins -> Red
8 Pins -> Green
8 Pins -> Blue
1 Pin -> Horizontal Sync
1 Pin -> Vertical Sync
This is the minimal signals you need in vga 8+8+8+1+1=26, but in a digital signal only uses 8 signals, the wrapper used could give 30bits but the implementation only gives 24bits, so 2 signals added for each RGB Color signals.
So for max1000 is more suitable a digital video signal.
You can see the impact in the utilization by entity of using a video signal compatible with DVI.
Code Select
set_location_assignment PIN_H6 -to SYS_CLK
set_location_assignment PIN_H5 -to TMDS[0]
set_location_assignment PIN_K10 -to TMDS[1]
set_location_assignment PIN_H13 -to TMDS[2]
set_location_assignment PIN_J13 -to TMDS[3]
set_location_assignment PIN_K11 -to TMDS[4]
set_location_assignment PIN_K12 -to TMDS[5]
set_location_assignment PIN_J12 -to TMDS[6]
set_location_assignment PIN_L12 -to TMDS[7]
You can see the pin planner in the photo added.
It is a nice thing to have a 24 or 30 bit color scheme an consumes a very low count kles.
There is a screenshot also of the compiled piotr-go-vga, but consumes only 8 pins.
In order to reproduce a vga signal with 24bits.
You need:
8 Pins -> Red
8 Pins -> Green
8 Pins -> Blue
1 Pin -> Horizontal Sync
1 Pin -> Vertical Sync
This is the minimal signals you need in vga 8+8+8+1+1=26, but in a digital signal only uses 8 signals, the wrapper used could give 30bits but the implementation only gives 24bits, so 2 signals added for each RGB Color signals.
So for max1000 is more suitable a digital video signal.
You can see the impact in the utilization by entity of using a video signal compatible with DVI.
#43
MAX1000 community projects / Re: Playing ZX Spectrum in HDM...
Last post by Subcritical - January 10, 2025, 02:40:41 PMUsing an DVI signal in 24bit color an late runs a ZX Spectrum.
The demo is located here for CYC1000, adapt it to MAX1000, is fairly easy.
https://github.com/AtlasFPGA/Demo_PIOTR.GO_888_DVI
The demo is located here for CYC1000, adapt it to MAX1000, is fairly easy.
https://github.com/AtlasFPGA/Demo_PIOTR.GO_888_DVI
#44
Arrow USB Programmer2 / Re: Step-by-step videos solvin...
Last post by Subcritical - January 10, 2025, 02:23:50 PMIN LINUX:
First uncompress the file of the arrow programmer.
Create a carpet with the content of the file provided.
Copy the file libjtag_hw_arrow.so into the linux directory that contains quartus ii web and move into ---route----quartus----ii-----web----/linux64
We need put inside this place the file with the .so extension -----file-----.so
In the direction of linux:
Create the file:
With this content:
You can finish the session "easy way".
An try this configuration for arrow blaster ii.
First uncompress the file of the arrow programmer.
Create a carpet with the content of the file provided.
Copy the file libjtag_hw_arrow.so into the linux directory that contains quartus ii web and move into ---route----quartus----ii-----web----/linux64
We need put inside this place the file with the .so extension -----file-----.so
Code Select
/usr/local/intelFPGA_lite/22.1std/quartus/linux64In the direction of linux:
Code Select
/etc/udev/rules.d/Create the file:
Code Select
51-arrow-programmer.rulesWith this content:
Code Select
# Arrow-USB-Programmer
SUBSYSTEM=="usb",\
ENV{DEVTYPE}=="usb_device",\
ATTR{idVendor}=="0403",\
ATTR{idProduct}=="6010",\
MODE="0666",\
NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}",\
RUN+="/bin/chmod 0666 %c"
# Interface number zero is a JTAG.
SUBSYSTEM=="usb",\
ATTRS{idVendor}=="0403",\
ATTRS{idProduct}=="6010",\
ATTR{interface}=="Arrow USB Blaster",\
ATTR{bInterfaceNumber}=="00",\
RUN="/bin/sh -c 'echo $kernel > /sys/bus/usb/drivers/ftdi_sio/unbind'"You can finish the session "easy way".
An try this configuration for arrow blaster ii.
#45
Arrow USB Programmer2 / Re: Step-by-step videos solvin...
Last post by Subcritical - January 10, 2025, 02:08:29 PM One of the problems that arise when you move the carpet/drawer, the original path you give to windows in the instalation of quartus. You move also were is located the service JTAG, because it tries to search in the original place you install QUARTUS II WEB.
Is a silly problem, but a common one that you change the place of the instalation manually.
In that case you can see that the problem could be seen in the Service manager as follows.
There are to solutions, move the directory of QUARTUS to the install directory.
Or alter the path of the server inside the Service Manager.
Mostly is a headache to note that silly fail...
Is a silly problem, but a common one that you change the place of the instalation manually.
In that case you can see that the problem could be seen in the Service manager as follows.
There are to solutions, move the directory of QUARTUS to the install directory.
Or alter the path of the server inside the Service Manager.
Mostly is a headache to note that silly fail...
#46
Arrow USB Programmer2 / Re: Step-by-step videos solvin...
Last post by Subcritical - January 10, 2025, 02:02:25 PMThe next step is open the services manager of windows.
The spetps are:
Frist go to the start menu.
Second go to Execute.
And type:
The spetps are:
Frist go to the start menu.
Second go to Execute.
And type:
Code Select
services.msc #47
Arrow USB Programmer2 / Re: Step-by-step videos solvin...
Last post by Subcritical - January 10, 2025, 01:52:32 PMThe first thing is open the CMD in windows an see if the server JTAG is available.
You need to search the name "Altera JTAG Server" listed like the image does.
Code Select
net startYou need to search the name "Altera JTAG Server" listed like the image does.
#48
Arrow USB Programmer2 / Re: Step-by-step videos solvin...
Last post by Subcritical - January 10, 2025, 01:38:24 PMFirst donwload the windows driver i use the version 2.5:
Select Driver 2.5
We must see the server JTAG, so the service that controls the incredible FTDI FT2232H at 20Mhz with the v2.5 driver. Notice that in the FT2232H the last consonant H means high speed, those modes could be developed in the future.
We must see the windows register to notice that all the parameters are correct.
So again we have the diagnosys tool from Arrow.
I up all the data we need.
In the last topic i will search inside the trenz website.
But is more confortable to habe all the stuff in the same thread.
Select Driver 2.5
We must see the server JTAG, so the service that controls the incredible FTDI FT2232H at 20Mhz with the v2.5 driver. Notice that in the FT2232H the last consonant H means high speed, those modes could be developed in the future.
We must see the windows register to notice that all the parameters are correct.
So again we have the diagnosys tool from Arrow.
I up all the data we need.
In the last topic i will search inside the trenz website.
But is more confortable to habe all the stuff in the same thread.
#49
Arrow USB Programmer2 / Re: Step-by-step videos solvin...
Last post by Subcritical - January 10, 2025, 01:22:24 PMI'm going to translate into english the solutions seeing in this Spanish Fpgaforum.
The title in Spanish is:
"ARRROW BLASTER - SOLUCIONAR PROBLEMAS EN SU INSTALACIÓN EN QUARTUS II"
http://www.forofpga.es/viewtopic.php?t=473
The title in Spanish is:
"ARRROW BLASTER - SOLUCIONAR PROBLEMAS EN SU INSTALACIÓN EN QUARTUS II"
http://www.forofpga.es/viewtopic.php?t=473
#50
Trenz Electronic FPGA Modules / Documentation inconsistencies ...
Last post by Gabriel - January 09, 2025, 09:51:32 AMHello,
I'm designing a base board for a TE0720 module, taking inspiration from the TE0703 for some parts (Ethernet jack and FT2232). But I believe I have spotted a few mistakes in the documentation.
By far the most serious one is the power supply voltage range accepted for Bank 34: the schematics page 19 claims that it accepts an I/O voltage range of 1.2 to 3.3V, the TRM gives a slightly different range (1.25 to 3.3V).
Xilinx/AMD requires the VCCOs to be within 5% of their nominal value: which would be 1.26V max in that case.
This already reduces the range to a very tight 10mV (1.25 to 1.26V), something which is very difficult, if not impossible, to achieve.
In the schematics, there is a TPS3805H33 (which I used in one of my designs) voltage detector which detects the presence of the VCCIO34 supply on it sense pin. The documentation of said chip indicates that its negative-going threshold is 1.226V, with a typical (no min nor max given) hysteresis of 15mV, so the positive-going threshold is nominally 1.241V, but the documentation gives a dispersion of the threshold of ±18mV. So the worst case would be 1.259V, leaving a margin of only 1mV to allow the TE0720 to proceed with booting. At that point it becomes sensitive to external factors, like temperature (the thresholds have a tendency to rise at low temperatures).
Even when fulfilling the TRM requirements (1.25V), a shift of 9mV in the TPS3805H33 threshold (half the guaranteed dispersion) would prevent booting.
Finally, in the TPS3805H33 documentation, there is also a specification of the propagation delay versus overdrive voltage, the table value is meaningless (uses 5% overdrive/underdrive) for the case discussed here and figure 13 does not accurately show what happens at very low overdrive voltages, so I don't think it can be used here. It just still lowers my confidence in the possibility to use 1.2V IO standards for bank 34.
For these reasons, I seriously doubt that it is possible to design a TE0720 baseboard that reliably boots when VCCIO34 is 1.2V, even when tweaking the supply close to the maximum. It is playing with fire; I need a 1.2V bank in my design, and I have excluded bank 34.
The other documentation glitches/inconsistencies are much less serious:
- the schematics on page 19 claim that VCCIO13 is mandatory, but the TRM does not mention it and I believe it's not needed
- on the top right side of page 5, between the "PWR IN" and "PWR out" labels, there are 4 "CLK" labels for group3. Apparently they moved there by accident, and they should be associated with B35 L11 and L14 FPGA pins.
I'm designing a base board for a TE0720 module, taking inspiration from the TE0703 for some parts (Ethernet jack and FT2232). But I believe I have spotted a few mistakes in the documentation.
By far the most serious one is the power supply voltage range accepted for Bank 34: the schematics page 19 claims that it accepts an I/O voltage range of 1.2 to 3.3V, the TRM gives a slightly different range (1.25 to 3.3V).
Xilinx/AMD requires the VCCOs to be within 5% of their nominal value: which would be 1.26V max in that case.
This already reduces the range to a very tight 10mV (1.25 to 1.26V), something which is very difficult, if not impossible, to achieve.
In the schematics, there is a TPS3805H33 (which I used in one of my designs) voltage detector which detects the presence of the VCCIO34 supply on it sense pin. The documentation of said chip indicates that its negative-going threshold is 1.226V, with a typical (no min nor max given) hysteresis of 15mV, so the positive-going threshold is nominally 1.241V, but the documentation gives a dispersion of the threshold of ±18mV. So the worst case would be 1.259V, leaving a margin of only 1mV to allow the TE0720 to proceed with booting. At that point it becomes sensitive to external factors, like temperature (the thresholds have a tendency to rise at low temperatures).
Even when fulfilling the TRM requirements (1.25V), a shift of 9mV in the TPS3805H33 threshold (half the guaranteed dispersion) would prevent booting.
Finally, in the TPS3805H33 documentation, there is also a specification of the propagation delay versus overdrive voltage, the table value is meaningless (uses 5% overdrive/underdrive) for the case discussed here and figure 13 does not accurately show what happens at very low overdrive voltages, so I don't think it can be used here. It just still lowers my confidence in the possibility to use 1.2V IO standards for bank 34.
For these reasons, I seriously doubt that it is possible to design a TE0720 baseboard that reliably boots when VCCIO34 is 1.2V, even when tweaking the supply close to the maximum. It is playing with fire; I need a 1.2V bank in my design, and I have excluded bank 34.
The other documentation glitches/inconsistencies are much less serious:
- the schematics on page 19 claim that VCCIO13 is mandatory, but the TRM does not mention it and I believe it's not needed
- on the top right side of page 5, between the "PWR IN" and "PWR out" labels, there are 4 "CLK" labels for group3. Apparently they moved there by accident, and they should be associated with B35 L11 and L14 FPGA pins.