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#1
Trenz Electronic FPGA Modules / Re: TE0714-04-52I-7-B 125 MHz ...
Last post by Antti Lukats - January 13, 2026, 08:43:36 AM
Hi

yes my fault I found one oscillator in the BOM and assumed it is is.

The LVDS oscillator is in the BOM only as "125MH oscillator" there is no type at all.

We may assemble with different oscillator from difference manufacturer one choice is:

DSC1123CI2-125.0000T

#3
Trenz Electronic FPGA Modules / Re: TE0714-04-52I-7-B 125 MHz ...
Last post by gvzz - January 12, 2026, 02:46:23 PM
OK, thanks.

Simon
#4
Trenz Electronic FPGA Modules / Re: TE0714-04-52I-7-B 125 MHz ...
Last post by Antti Lukats - January 12, 2026, 02:26:37 PM
SIT8008BI-73-18S-25.000000E

Altium files for TE0714 we can not share.
#5
Trenz Electronic FPGA Modules / TE0714-04-52I-7-B 125 MHz osci...
Last post by gvzz - January 12, 2026, 12:21:00 PM
Hi,

I am planning to make my own TE0714 carrier card with at least 2 SFP and additional stuff on it.

The 125 MHz MGT oscillator for the MGT1 is mounted on board:

Screenshot 2026-01-12 121430.png

Would be possible to know its part number? The STM mark on my board is BTH R06 312.

Also, unlike the TE0714 Simple Base, there is not Altium board project for TE0714-04-52I-7-B.
Would it be possible to make it available for download?

Thanks,
Simon
#6
Trenz Electronic FPGA Modules / Re: TEI0006 clock synthetizer ...
Last post by Antti Lukats - January 08, 2026, 01:03:08 PM
please contact support email. A custom version of the CPLD firmware is needed to have different clocks.
#7
Trenz Electronic FPGA Modules / TEI0006 clock synthetizer conf...
Last post by guirenaud - January 05, 2026, 10:56:23 AM
Hello

I'll use the TEI006 SOM with custom mother board
I'd like to change the default clock synthetizer configuration.
I'd like to have on OUT2 a 40MHz LVDS output. By default it outputs 100MHz LVCMOS (signals CLK2_P and CLK2_N from schematics SCH-TEI0006-04-API23A.pdf)
Is it possible ?
I'd like to be able to order the SOM with that config. by default.
We have already ordered one, can we update it also by ourself ? Which procedure should we use ?

Sincerely
#8
Trenz Electronic FPGA Modules / Re: Description of pins on TE0...
Last post by remy - December 30, 2025, 10:21:01 AM
Understand, I will ignore them. Thank you!
#9
Trenz Electronic FPGA Modules / Re: Description of pins on TE0...
Last post by Antti Lukats - December 29, 2025, 04:40:21 PM
Hi,

if you look at schematic you see a RED CROSS on those wires, this is Altium desiger marking for exclusion from rules checking. This means that altium DRC passes and does not report single pin nets as error.

There is no internal connection on the board on those pins, you can simple ignore them, they used to be connected to some weird security chip in PCB rev 01
#10
Trenz Electronic FPGA Modules / Description of pins on TE0728
Last post by remy - December 29, 2025, 02:16:53 PM
Hi,

I'm making m y own carrier board to the TE0728 SoC Module and I'm not able to find description for the following pins:
J1.12 INTB
J1.14 RSTB
J1.16 FS0B
J1.15 MUX_OUT
J1.17 VCCA
J1.18 DEBUG
J1.20 LIN
J1.21 VSUP3_LIN

Would it be possible to get some inside into what these pins should/could/must be used for?

Thanks,