Recent posts

#21

Trenz Electronic FPGA Modules / Re: TE0720-04-62I33MA QSPI pro...

Last post by michalk - October 24, 2025, 10:38:44 AM

Thank you JH,
the workaroud worked just fine and it seems after initial flash I can reflash QSPI without any issues.

This allows me to confirm the module is fine, but now I need to move on to production environment where SD card is not supported by hardware.
What would be the workflow then? I have a working bin file for QSPI, a brand new module and only JTAG connection. Ideally the module would already be placed in a sealed chassis, but one time programming could be done earlier.

Having to do first flash on the dev board is an option but not very welcome, since module is already attached to a final device at the time the programming is required. As I mentioned I tried alternative fsbl earlier (on 2019.2) and it would not work for me this time (I programmed earlier modules some time ago during development with success) So this time I want to prepare an instruction for future production series that will work every time.

best regards,
Michal

#22

Trenz Electronic FPGA Modules / Re: SDCARD Images download for...

Last post by JH - October 24, 2025, 09:22:26 AM

Hi,
that's not the serial number I mean. Serial number should be on on the small white sticker with QR code on the module or on the cardboard box of the module.

 ...\prebuilt\boot_images\1qf_1gb\hello_te0720
this one is simple Hello World application in endless loop. It contains FSBL, bitstream and hello_trenz.elf, see bif file

 ...\prebuilt\boot_images\1qf_1gb\u-boot

this boot bin is for linux and contains FSBL, bitstream and uboot.
Uboot search for linux files on the SD card. So put boot.scr, image.ub on SD card. device tree is included into the image.ub

br
John

#23

Trenz Electronic FPGA Modules / PS->PL EMIO 1 GbE to SFP for T...

Last post by paul - October 23, 2025, 11:56:16 PM

The design uses Vivado 2023.2 and instantiates the PCS/PMA IP Core in 1000BASE-X mode which is connects to an SFP/SFP+ module installed on the carrier. The GEM GMII and MDIO is connected to the PCS/PMA core viea EMIO.

With an SFP+ 0 dB loopback module installed: https://www.10gtek.com/sfploopback
the Linux kernel is happy and tcpdump shows the transmitted packets successfully being received.

Code Select Expand

Configuring network interfaces... macb e000b000.ethernet eth0: PHY [e000b000.ethernet-ffffffff:01] driver [Xilinx PCS/PMA PHY] (irq=POLL)
macb e000b000.ethernet eth0: configuring for phy/gmii link mode
done.
macb e000b000.ethernet eth0: unable to generate target frequency: 125000000 Hz
macb e000b000.ethernet eth0: Link is Up - 1Gbps/Full - flow control off
IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
And looped-back packets:

Code Select Expand

# tcpdump -r pkt_loopback_sfp.pcap
reading from file pkt_loopback_sfp.pcap, link-type EN10MB (Ethernet), snapshot length 262144
19:18:52.589688 ARP, Request who-has 192.168.1.221 tell 192.168.1.220, length 28
19:18:52.589762 ARP, Request who-has 192.168.1.221 tell 192.168.1.220, length 46
19:18:53.593173 ARP, Request who-has 192.168.1.221 tell 192.168.1.220, length 28
19:18:53.593226 ARP, Request who-has 192.168.1.221 tell 192.168.1.220, length 46
19:18:54.633168 ARP, Request who-has 192.168.1.221 tell 192.168.1.220, length 28
19:18:54.633222 ARP, Request who-has 192.168.1.221 tell 192.168.1.220, length 46
19:18:56.590178 ARP, Request who-has 192.168.1.221 tell 192.168.1.220, length 28
19:18:56.590235 ARP, Request who-has 192.168.1.221 tell 192.168.1.220, length 46
19:18:57.593172 ARP, Request who-has 192.168.1.221 tell 192.168.1.220, length 28
19:18:57.593227 ARP, Request who-has 192.168.1.221 tell 192.168.1.220, length 46
19:18:58.153179 IP6 fe80::fe0f:e7ff:fe21:3703 > ip6-allrouters: ICMP6, router solicitation, length 16
19:18:58.153237 IP6 fe80::fe0f:e7ff:fe21:3703 > ip6-allrouters: ICMP6, router solicitation, length 16
19:18:58.633170 ARP, Request who-has 192.168.1.221 tell 192.168.1.220, length 28
19:18:58.633219 ARP, Request who-has 192.168.1.221 tell 192.168.1.220, length 46

The problem occurs when I attempt to communicate with another board. I have tried a 1000BASE-T SFP module, multimode fiber SFP+ module, and a passive DAC twinax cable all with the same failed result:

• System only detects a link if autonegotiation is disabled with ethtool
• Regardless of the autonegotiation setting, no packets are successfully transmitted or received on either end with the TE0715 in the loop.
• I put an ILA on the transceiver status signals from the PCS/PMA core, and see RXNOTINTABLE errors occurring, followed by the link being reset periodically

I instantiated Xilinx's example 1G PS EMIO 1000BASE-X design on a ZCU-102 to communicate with on the other end. These same SFP/SFP+ modules in the ZCU-102 link up fine with a Mikrotik switch, but no luck with the TE0715 at the other end.

I used counters to measure the ratios of the clock signals from the synthesizer on the TE0715 and they look right. Do I need to program the clock synthesizer explicitly?
Any ideas to look at?

Thanks!
Paul

Devicetree:

Code Select Expand

&gem0 {
/delete-property/ local-mac-address;

nvmem-cells = <&eth_addr>;
nvmem-cell-names = "mac-address";

status = "okay";
compatible = "cdns,zynq-gem", "cdns,gem";

phy-mode = "gmii";
phy-handle = <&ethernet_phy1>;

mdio {
#address-cells = <1>;
#size-cells = <0>;

ethernet_phy1: ethernet-phy@1 {
reg = <1>;
xlnx,phy-type = <0x5>;
/* sfp = <&sfp0>; */
};
};
};


#24

Trenz Electronic FPGA Modules / Re: SDCARD Images download for...

Last post by eddydw - October 23, 2025, 06:21:39 PM

Hi John,

I assume that the serial number is E220282 (ML-02Z),
The carrier is TE0701-06 and the SOM is TE0720-04.


It would help if you could explain the file_location.txt file content.

The pre-built folder/os/petalinux/1GB does not have a boot.bin.
It has 4 files : boot.scr, image.ub, system.dtb and u-boo.elf.
Which boot.bin should I copy onto the SC CARD?

When looking in the pre-built folders there are multiple boot-bin files . So which one to choose. There is one in :
- ...\prebuilt\boot_images\1qf_1gb\hello_te0720
- ...\prebuilt\boot_images\1qf_1gb\u-boot

So It would be great if you could be very specific.

Thanks in advance
Eddy

#25

Trenz Electronic FPGA Modules / Re: SDCARD Images download for...

Last post by JH - October 23, 2025, 08:07:11 AM

Hi,

binaries to boot directly from SD are included into the reference design. Put Boot.bin and corresponding linux files(image.ub boot.scr) on the SD card with a fat32 partition.
Needed binaries depends on you TE0720 assembly variant. Check prebuilt\file_location.txt to find the correct one for your assembly variant or start scripts and select binary export:
https://wiki.trenz-electronic.de/display/PD/TE0720+Reference+Design#TE0720ReferenceDesign-Getprebuiltbootbinaries

In case I should help to select correct files, please send me the serial number of your TE0720 module and I check which assembly variant you has bought.

br
John

#26

Trenz Electronic FPGA Modules / Re: LEDs on TE0701 + TE0720

Last post by eddydw - October 22, 2025, 04:30:49 PM

Hi Manuela,

I have set SW4 and SW3 as follows :

S4[4..1] = [OFF,OFF,OFF,OFF]
SW3[4..1] =  [OFF,ON,OFF,ON]

Question 1 : According to the TRM-TE0701 pdf table on page 24  this means that VID2,VID1,VID0 are 000 and this FMCVADJ is 3.3V correct?

Since S4-4 (CM2) = OFF ==> PGOOD = 1

When SDCARD is inserted MODE = 0
==> Boot Mode = SD card Mode since PFOOD=1 and MODE=0 (according to https://wiki.trenz-electronic.de/display/PD/TE0701+CPLD#TE0701CPLD-PCBREV06)
However there is a note (on page 24) that says "SC CPLD settings will be overridden by DIP switch S4, if one of them is set to one (OFF position)"

Question : Does this mean that OFF = 1 and ON=0 ?

The table on page 25 is very confusing.


Bottom line : We would like to be able to boot from SDCARD and also see the UART output on a terminal. The MIO14 and MIO15 pins are connected to the FTDI IC. The documentation refers to UART1 on the Zynq 7020,but that is wrong. It is actually UART0!
I have changed the UART from UART1 to UART 0 in the reference design but we still cannot see anything on the UART terminal too (by using a simple Hello World baremetal application),so we suspect that there is still a missing setting.


We would appreciate it if you could give us the settings of the DIP SWITCHES S3 and S4 and other neccesary settings (like for example JUMPERS) on the TE0701 carrier board in order to be able to boot from SDCARD and to be able to see the UART to.


I have created a bootable SDCARD Image with petalinux. I want to test it but I need to have a working UART,but since there is still no output on the UART I am blocked as the UART terminal is needed to view the logging of the boot process.


Please help? We have been stuck for a few weeks.
Can we eventually have a direct contact by gorkys@telenet.be

#27

Trenz Electronic FPGA Modules / Re: SDCARD Images download for...

Last post by eddydw - October 22, 2025, 04:26:20 PM

Are there no SD card image files that are ready to flash directly on an SDCARD?

#28

Trenz Electronic FPGA Modules / Re: Petalinux boot from the on...

Last post by JH - October 21, 2025, 09:43:47 AM

Hello AlexSan,
how did you set your device tree for QSPI flash? Did you add the same like we in our reference design?

Code Select Expand

&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
       
        spi-rx-bus-width = <4>;
        spi-tx-bus-width = <4>;
        spi-max-frequency = <90000000>;
    };
};

br
John

#29

Trenz Electronic FPGA Modules / Re: TE0720-04-62I33MA QSPI pro...

Last post by JH - October 21, 2025, 09:27:12 AM

Hi,
yes alternative FSBL for Flash programming does not longer work with newer Vivado versions.

Can you try out following workaround (this was working on my place):
Put the Hello TE0720 boot.bin on SD Card and boot from SD (SD card must be inserted to switch mode). When it boots connect HW Manager and try to configure QSPI again.

On newer TE0705-4 together with TE0720 newest CPLD firmware, we add possibility to change boot mode to JTAG only for QSPI programming.

If you still have problems with this workaround,
there is also an alternative firmware for TE0705-3 available, which can be used to set JTAG boot mode temporary (https://wiki.trenz-electronic.de/display/PD/TE0705+CPLD#TE0705CPLD-PCBREV03(Optional).1). In this case you need to update your TE0705 CPLD and maybe your TE0720 CPLD (depending how old it is, newest CPLD Firmware was released June 2022, so it must be newer.).
If the workaround doesn't work, let me know and I help you to update firmware.


br
John

#30

Trenz Electronic FPGA Modules / TE0720-04-62I33MA QSPI program...

Last post by michalk - October 17, 2025, 12:21:27 PM

I have issues consistently programming above SoM.
Some time ago I created an aplication for the said module and (not without issues) managed to flash it onto module using Vivado 2019.2.
Now I needed to repeat this but was unable to use previous flow - for some reason modified FSBL did not work for me anymore with same binaries.
I decided to test how newer version of Vivado work. The project was ported to 2024.2 and still I was unable to program QSPI.

I took the step back, placed my SoM onto TE0705-03 eval board and tried to run the TestBoard example - and I still am unable to flash QSPI.
I even tried 2023.2 Vivado and example, but the result is the same:

Code Select Expand

TE::pr_program_flash -swapp hello_te0720
Start Flash Programming
INFO: [Labtools 27-1435] Device xc7z020 (JTAG device index = 1) is not programmed (DONE status = 0).
WARNING: [Labtoolstcl 44-653] Creating new cfgmem for device xc7z020_1 will delete cfgmem object cfgmem_2 currently associated with it.
INFO: [Labtools 27-1435] Device xc7z020 (JTAG device index = 1) is not programmed (DONE status = 0).
WARNING: [Xicom 50-100] The current boot mode is QSPI.
Flash programming is not supported with the selected boot mode.If flash programming fails, configure device for JTAG boot mode and try again.
Problem in Initializing Hardware
Flash programming initialization failed.
ERROR: [Labtools 27-3161] Flash Programming Unsuccessful
ERROR: [TE_PR-108] Script (TE::VLAB::hw_program_flash) failed: ERROR: [Common 17-39] 'program_hw_cfgmem' failed due to earlier errors.
This is done in completely fresh installation of Vivado 2023.2, using freshly downloaded example (2023.2 version) generated for Som number 66 - TE0720-04-62I33MA. The result does not vary depending on whether SD Cards is inserted.

What may possibly be wrong if I can't even get reference design to flash QSPI on my module? I will be glad for any pointers.