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#21
Trenz Electronic FPGA Modules / Re: TE0722 not detected by viv...
Last post by JH - October 18, 2024, 09:05:46 AM
Hi,
TE0790 use MIC5504-3.3YMT with max 0.3A so I think is not powerfull enough.

QuoteVoltages: When connected to the external supply (no USB connected) I tried to measure between the power supply ground and the 3.3V pin next to pin A (on the getting started schematic) and the boards lights turned off... Which is concerning. Despite all that the board is still detected when powered by the USB and not when powered by external.
that's very strange. QSPI was programmed or not programmed before? In case it's not programmed, only done led(Red LED) should be on in case it's not programmed. And this light goes off when you try to measure?
On my older TE0722, I've 240mA and 320mA in case USB is connected. SoC is not programmed in this case.
From test reports new versions has ~ 170mA in case it's not programmed.

LED was going off but you could measure 3.3V, correct?
Did you try out another channel of your laboratory power supply?

You can also try to supply it from both, XMOD and your laboratory power supply.

Note: On TE0722-04 there is a additional connector footprin J4, near the lable, when you short this pin, than you has JTAG only boot mode where system doesn't boot from qspi, it's easier for QSPI programming and recovering in case boot process crashed and you can't get access.
br
John






#22
Trenz Electronic FPGA Modules / TE0720 - Ethernet with LWIP an...
Last post by Bengs - October 17, 2024, 12:49:18 PM
Hello Everyone,

I send this post because I encounter a problem on my TCP Server on my TE0720-04-62I33ML Board. I try to find some information on AMD, Stack forum but anyone reply me. I try to realize a 1Gb Ethernet with LWIP, I follow all wiki or document I find on this library and method to implement this fucntionnality.

Moreover, I realize with success to transfer data from my pc (winsock2) and my server on zynq to change several parameters or data on the board like delay, ip address etc ...

But my problem is when I try to send more data from my PL Ping-Pong Fifo. Currently my TCP windows (65 535 bytes in size) becomes full after 1-2 seconds. I try to implement a tcp_sent/tcp_poll and tcp_tmr for flag but nothing resolves my problem.

I give you a scheme of my current architecture of the server and a picture from the server, the client and finally a wireshark picture. I don't know how to pass this difficulty.


My last idea in order to resolve my problem consist of separate the PS ethernet with the command for the measure and the PL Fifo to avoid material interruption (-> others problems because this kind of interruption interrupts the tcp callback function in my PS) & to optimize throughput in the PL directly by adding a bigger tcp windows. I don't how to implement this and if this kind of things can work.

In all cases, thanks for your future reply and if you want you can contact me directly by mail. I wish you a good day.

Best,

Benjamin Laforêt.

(PS: I cannot send all my picture in one )

#23
UltraScale / Re: AMD Zynq™ UltraScale+™ ZU1...
Last post by JH - October 16, 2024, 11:11:46 AM
Hi,

XCZU1EG was not available as Xilinx published Vivado 2019.2. So Vivado 2019.2 does not support this device.


I would recommend to use Vivado 2022.2 (ZU1 is available in the free Vivado ML Standard Edition) and start with our reference design, which based on 22.2 Version:

    https://wiki.trenz-electronic.de/display/PD/TE0802+Test+Board
        https://wiki.trenz-electronic.de/display/PD/TE0802+Test+Board#TE0802TestBoard-Download

br
John
#24
Trenz Electronic FPGA Modules / Re: TE0722 not detected by viv...
Last post by vertapple - October 13, 2024, 10:24:14 PM
Hello, unfortunately I'm back. I only recently went back to the lab and attempted to try some of your suggestions.

Pin setup: It's still the same as before and as far as I'm aware it's fully correct according to the getting started page.

Voltages: When connected to the external supply (no USB connected) I tried to measure between the power supply ground and the 3.3V pin next to pin A (on the getting started schematic) and the boards lights turned off... Which is concerning. Despite all that the board is still detected when powered by the USB and not when powered by external.

I also tried leaving it powered for a while before connecting a USB and that didn't work either.
Weirdly though, when powered without the USB connected, it draws 0.16A. Connecting the USB it would go up to 0.18A, then after disconnecting it, it would go down to 0.12A? seemed a bit strange.

This is for my honours thesis, my due date is in 3 weeks so I'm rather desperate to get it working. I'm going to attempt the recovery process one more time but if that does not work I'd like to know how risky it is to run the SoM on the XMOD? I have a rather large design (I do not know the metrics to measure the size of an FPGA design but I'm using 74% LUTs and about 1W power excluding the external camera module) so I imagine it would not end well.

I appreciate the help you've given thus far.
regards.
#25
UltraScale / AMD Zynq™ UltraScale+™ ZU1EG a...
Last post by mariem - October 11, 2024, 10:55:52 AM
Hello,

I recently acquired a development board with the AMD Zynq™ UltraScale+™ ZU1EG and 1 GB LPDDR4(Model TE0802-02-1BEV2-A). However, I am having trouble finding the part number "XCZU1EG-1SBVA484E7100" in the list of parts available in Vivado 2019.2.

Could you please confirm the correct part number to use for this board in Vivado or let me know if there is an update or specific configuration needed for this model?

Thank you in advance for your assistance.

Best regards,
Mariem
#26
Could you please update Assembly Diagrams for TE0701-06 board aka AD-TE0701-06.pdf file with with positions of M2.5 FMC holes, those two near edge of card?

I compared AD-TE0701-06.pdf with AD-TE0701-05.pdf some distances are same, some are off by 0.02mm (which is Ok), but FMC hole near S3 switch is on x-axis off by 1.5mm (maybe mistake), while y-axis distance does not exists.
Also FMC hole near L8 do not have any distances assigned (assume that y-axis distance is same as one of hole near S3).
Considering that even M3 hole changed position between AD-TE0701-06.pdf and AD-TE0701-05.pdf (kind a strange to move them, maybe also mistake, maybe you move them bcs were on the way of power supply), I have pretty low confidence to numbers given in AD-TE0701-05.pdf, so I pledge you to update AD-TE0701-06.pdf.

I have hard time to measure all this, especially 0.2mm tolerance for typical 2.7mm hole M2.5 for FMC.

Similar problem already existed on earlier version of TE0701:
https://forum.trenz-electronic.de/index.php?topic=300.0


Thanks in advance.
#27
Trenz Electronic FPGA Modules / Re: TE0715 new reference desig...
Last post by Swiss222 - October 09, 2024, 10:54:54 AM
Hi, thank you for your answer!

This topic is still very confusing to me, I would appreciate if you understand this better and could answer me:

People keep talking about Yocto vs. Petalinux but I don't see how this makes any difference when talking about security updates. From my perspective, the main issue is the linux kernel that Xilinx provides (https://github.com/Xilinx/linux-xlnx) and updating it in the project.
Both are possible in both petalinux as well as yocto if I am not mistaken? Is it maybe easier to update with pure Yocto?

I followed these steps (https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/757891119/Migrate+from+PetaLinux+project+to+Yocto+project#Importing-Petalinux-Project-into-Yocto-Project) to migrate my petalinux project into a yocto project and I don't see how that will make the updating process easier for me.

I have to ask the same question in Xilinx's forum but maybe you could already clarify some points for me.

Thank you.
#28
Trenz Electronic FPGA Modules / Re: TE0715 + TE0701 Board Prog...
Last post by JH - October 09, 2024, 09:09:59 AM
Hi,
program flash of 7 series zynq with newer Vivado tools is not longer so easy when boot mode is not JTAG only. Here are some notes about this topic:
https://wiki.trenz-electronic.de/pages/viewpage.action?pageId=105689937

We start to update CPLDs of the 4x5 modules and carriers to use PGOOD signal of the module as additional boot mode pin.
TE0715 supports this since the middle of the last year, TE0701 carrier CPLD is currently in development for an update.
In case your TE0715 is older, than It's unfortunately not possible to update Module CPLD with TE0701, it's planned to add this feature in the next PCB Update of TE0701.

The easiest way for you is at the moment to download Vivado Labtool 2017.2 and use this to program:
https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/archive.html
-->https://www.xilinx.com/member/forms/download/xef.html?filename=Xilinx_Vivado_Lab_Win_2017.2_0616_1.tar.gz
In this case separate FSBL is not needed, only Boot.bin must be set inside Hardware manager. QSPI Flash type is in the most cases "s25fl256s-3.3v-qspi-x4-single" (see test_board\board_files\TE0715_board_files.csv)
In case you has still trouble, send me the serial number of the module and I check if you has select correct files.
br
John
#29
Trenz Electronic FPGA Modules / TE0715 + TE0701 Board Program ...
Last post by Jason_Baxter - October 08, 2024, 02:02:16 PM
Hello,

I have issues writing the flash to the TE0715 mounted on a TE0701 board. I have created an FSBL, imported the prebuilt 04_30_3e_1gb, built the project, created a boot image and then connected the JTAG via mini-USB. I am trying to flash using qspi-x4-single but get the following error. The progress bar hangs and nothing happens. The dip switch (S3-3) is set to the Xilinx chip (on TE0701) and not the CPLD. The board is powered via the 12V supply. I'm unsure what else to do and am looking for guidance. Please let me know if there is any more key information I can provide.

Thank you.

****** Xilinx Program Flash
****** Program Flash v2022.2 (64-bit)
  **** SW Build (by xbuild) on 2022-10-13-12:09:39
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.


WARNING: Failed to connect to hw_server at TCP:127.0.0.1:3121
Attempting to launch hw_server at TCP:127.0.0.1:3121

Connected to hw_server @ TCP:127.0.0.1:3121

Target not specified. Selecting target_id 2 (arm_dap) by default.

Retrieving Flash info...

Initialization done
Using default mini u-boot image file - C:/Xilinx2022/Vitis/2022.2/data\xicom\cfgmem\uboot\zynq_qspi_x4_single.bin
===== mrd->addr=0xF800025C, data=0x00000001 =====
BOOT_MODE REG = 0x00000001
WARNING: [Xicom 50-100] The current boot mode is QSPI.
Flash programming is not supported with the selected boot mode.If flash programming fails, configure device for JTAG boot mode and try again.
#30
Trenz Electronic FPGA Modules / Re: TE0722 not detected by viv...
Last post by JH - October 08, 2024, 11:04:47 AM
Hi,
primary boot from SD is not possible, because of the small FPGA package with less IOs.
What you can do later is program QSPI with an FSBL which is modified to search bitstream and other files from SD(change boot mode inside fsbl code instead using boot mode pins, he should use fix sd and put second boot.bin with bitstream to SD card. In this case PS Konfiguration depends always from your QSPI FSBL version).
Application will be more difficult later, because TE0722 is without RAM, so you need to put it into OCM or block ram or xip: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/2418900993/Zynq+7000+Tips+and+Tricks#Execute-In-Place-(XIP)

br
John