Ethernet does not work correctly on QSPI flash program in TE0729

[david.sakharov]

Hi
im using te0729 with its carrier board teb729 on my project
i design my project hardware in vivado 2019.1 with some change in prebuilt project in te0729 refernce design and export it to sdk.
i implement bsp with lwIP and run my standalone application on sdk debugger.
everything works fine.all 3 Ethernet and other peripherals works correctly.
but
when i program qspi flash with my application and boot from it,the axi-ethernetlite modules doesn't work correctly.it stack on setup-netif(); functions and application doesn't go any further.
i create my fsbl project and enable its debuge info.when i check the fsbl debugger it shows it run correctly and my application run after boot sequence.i also checked ps7-init and ps7-post-config are run in fsbl sequence
i dont know what else to do.
ill be thankful for the helps
best regards

[JH]

Hi,
did you built elf as debug or as release in your Boot.bin version?
Maybe you should also write one time to Xilinx forum, this looks like an lwIP stack problem and Xilinx community is much bigger.

br
John

[david.sakharov]

hi john, thanks for the reply
i did run my application in both debug and release version,both works fine in sdk debugger.
and i use both of them on my .bin file,none of them didn't work.
and about lwip ,i dont think so it will bug in lwip because it work in debugger runs.
best
david

[JH]

Hi,

and i use both of them on my .bin file,none of them didn't work.

did you generate the FSBL also from this vitis project with from the same xsa file?

and about lwip ,i dont think so it will bug in lwip because it work in debugger runs.

that's the big question...why it should be some other bug?
I've seen this from time to time on Xilinx software(for example QSPI programming on native FPGA). Initialisation differs something between the different boot modes. Maybe Lwip expect PHY in another state and fsbl and script version will configure PHY differently or the point of time where your application starts after initialisation and get access to phy differs....

I think you should also ask on Xilinx forum, maybe somebody else has the same issue with LWIP and can give you some hints. I use only Linux...so I can't help much with LWIP

br
John

[david.sakharov]

hi jonh

Hi,did you generate the FSBL also from this vitis project with from the same xsa file?

i generate FSBL with same xsa file for both of them .i did it in sdk 2019.1 .
i also test the fsbl file from the trenz te0729 reference design with my project,it doesnt work ether.

I've seen this from time to time on Xilinx software(for example QSPI programming on native FPGA). Initialization differs something between the different boot modes. Maybe Lwip expect PHY in another state and fsbl and script version will configure PHY differently or the point of time where your application starts after initialization and get access to phy differs....

i am agree too.because i did some changes in lwip source file (x_topology_c.c) so i can work with all 3 ethernet at same time.
i have to ask them too.
but i have a question.
when i configure a run for my project,it says that it do the following sequence:
1.program fpga
2.run ps7_int
3.run ps7_post_config
4.rum my application
but i check fsbl project,it run ps7_post_config when it want to handoff to application,
thats my question do you think would it be the problem?
meanwhile i change the fsbl to run ps7_post_config  before application,it didnt work.
Regards
david

[JH]

Hi,

thats my question do you think would it be the problem?
meanwhile i change the fsbl to run ps7_post_config  before application,it didnt work.

Maybe, I don't now.

What you can to maybe is to force ETH PHY reset on your IwIP application before IwIP initilise everything (one reset is connected to MIO and 2 resets are connected to PL, see schematics). Maybe this helps. Or/and check whats happens when you start initialisation of IwIP twice....I think it's try and error to find solution. You can also try following:
1. Put your Boot.bin with your IwIP app build as debug on SD card and set boot mode to SD.
2. Start debugger in SDK and set a breakpoint.
3.force module reboot.
With a little bit luck it will stop on this break point and you can step during your code which was executed from SD. Maybe it helps to debug it better?

br
John

[david.sakharov]

hi jonh
i run some test and i track down my application to find out whats going on.
in lwip library source in emacliteif.c file in function named "low-level-output"
the function use 2 macros when it want send out the data."sys-arch-protect(lev)" and "sys-arch-unprotect(lev)"
when the application reach "sys-arch-unprotect(lev)" it goes on halt and did not go further.
for some reason my xilinx account is block so i can't ask xilinxs to help .
meanwhile when i comment "sys-arch-unprotect(lev)" it go on the application but it stack on next outgoing packet
i do some search and learn about those macros but i dont know what exactly they do.
i have this question,do you know what do those macros do?

[JH]

Hi,
no sorry. I've no experience with IwIP.
I've searched shortly on Xilinx forum, maybe one of these posts help you:
https://support.xilinx.com/s/global-search/sys-arch-unprotect?language=en_US
they speak also about protect/unprotect --> https://support.xilinx.com/s/question/0D52E00006ksXpjSAE/ethernet-interrupt-stops-working-after-a-while?language=en_US

br
John

[david.sakharov]

hi Jonh
 i really thank you for your concern.
I've already read them.
i have some theory that i have to test them
 i will post the answer as soon as i find it
wish me luck
bests
david

[david.sakharov]

hi
i ran many tests.
when i use sdk example like udp client pref it work correctly.
but it work with only 1 Ethernet port.
i wish any trenz members can test 3 Ethernet on TE0729 with sdk 2019.1
i think i have to post a new topic for it
bests
david

[JH]

Hi,

i think i have to post a new topic for it

yes that's good.

I would suggest you make the same post also on Xilinx forum. community there is much bigger.

br
John

[david.sakharov]

******* BEST SOLUTION *******
hi
I finally find out the answer for my issue.i share the solution maybe it will be useful for others.
note that i test my solution with vivado/sdk 2019.1 version
i create the vivado project based on Trenz TE0729 board refer to below link
https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0729/Reference_Design
i create the hardware platform refer to bit file exported from above project.
after that i create board support package (bsp) projet with lwip211 with default value parameters.
then i modify the following file in lwip source files
1.in xpqueue.c file, i change NUM_QUEUES value from "2" to "8"
the  NUM_QUEUES  is at line 36 of xpqueue.c file
xpqueue.c file is located at ".../libsrc/lwip211_v1_0/src/contrib/port/xilinx/netif"
2.in xtopology_g.c file i change line 17 parameter "XPAR_FABRIC_AXI_ETHERNETLITE_0_IP2INTC_IRPT_INTR" to "XPAR_FABRIC_AXI_ETHERNETLITE_1_IP2INTC_IRPT_INTR"
the modification is changing 0 to 1 on above file.
 xtopology_g.c file is located at ".../libsrc/lwip211_v1_0/src/contrib/port/xilinx/netif"
then i create udp client prif project from application porject example menu and modify it for 3 ethernet interface
the modification is
1.add 2 mac address to project.
2.add 2 netif struct to project
3. add 2  xmac_add() function refer to 2nd and 3rd ehternet base address(refer to xparameter.h file)
4.add xemacps_input() for aded netif file.
note that for PS ethernet interface i create my own library an add it to the project.
i did it because lwip does not support Zynq ps Ethernet and axi_ethernetlite at same time
i hope this post would be help
best regards
david