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91
Trenz Electronic FPGA Modules / TE0720/TE0706 based design
« Last post by bigguiness on March 24, 2022, 09:45:36 PM »
Hello,

I'm working on a design using a TE0720 SoC that is based on the TE0706 carrier board since I require two Ethernet ports.

I have a couple questions on the block diagram of the te0720-eth706.xpr project.

1) Is the Concat/Labtools Frequency Counter/VIO/Utility Vector Logic part necessary or is that part of the block design strictly debug stuff?

2) Is the TE0720 System Controller I/O necessary? I assume that is is in order to connect the CPLD on the TE0720 to the Zynq. Is that IP available? When I start a new design I can't find it in the IP library.

3) I assume that the Constant block connected to the ETH_CONFIG[0:0] port is for the Ethernet PHY on the TE0720 and is needed. Correct?

4) I am a bit confused by the FCLK_CLK0 and FCLK_CLK1 outputs of the Zynq7 block. FCLK_CLK0 is set for 100MHz, FCLK_CLK1 is set for 200MHz. FCLK_CLK0 is only connected to the stuff in 1) above. FCLK_CLK1 is connected to the "slowest_sync_clk" of the Processor System Reset block and the "clkin" of the Gmii to Rgmii block for Ethernet 2. Shouldn't the Processor System Reset use the 100MHz clock?

Thanks for any help
92
Trenz Electronic FPGA Modules / Re: CPLL in GTH Transceiver on TE0803 board not locking
« Last post by JH on March 18, 2022, 08:20:05 AM »
Hi, GTH are enabled with TEBF0808 carrier and default CPLD Firmware.

As long as CPLL or QPLL not locked, you has a problem with reference CLK. TX RX loopback is no matter in this stage....maybe you has select wrong input or wrong frequency. Selected Reference CLK in this IP must match this one which is present on the selected CLK input pin. And this input clk freq. must be one of them which is be valid for GTH VCO. For Xilinx GTH mostly 125MHz(250MHz) or 156,25MHz(312,5MHz) will be used to support the most literates.

br
John
93
Trenz Electronic FPGA Modules / Re: TE720 pin state during/after startup
« Last post by JH on March 18, 2022, 08:10:46 AM »
Hi,
Quote
So during the startup all the pins of ZynQ have PULLUP enabled. But what happens later before my code starts the main() function (it's bare metal application)? Do the pins stay tristated without PULLUP until I do my system probing and setup SPI directions? The relevant pins are declared as INOUTs my project.
Before bitstream is configured, IOs will be pulled up with def. CPLD Firmware, after bitstream is configured with your bitstream it will be do what you has configured in your design, when you use PS SPI, see Zynq IP configuration.

br
John
94
Hi,
we normally share only source code of the carrier. Can you write a email to support@trenz-electronic.de an tell me why you need this source code? CPLD Description itself is here: https://wiki.trenz-electronic.de/display/PD/TE0745+CPLD
br
John
95
Could you please share the CPLD firmware source code of TE0745 module? We'd like to learn the codes. Thanks.

The JED file (SC-PGM-TE745-0102_SC0745-01_20160530.zip) could be downloaded from your website.

96
Trenz Electronic FPGA Modules / TE720 pin state during/after startup
« Last post by linasr on March 15, 2022, 11:14:33 AM »
Dear All,

I have multiple SPI masters in my system. One of them is TE720 module using SPI 0 block with EMIO pins and other is "normal" AXI Quad SPI. Microprocessor SPI masters share the same SPI buses and pins. I am afraid, that microprocessor and ZynQ might have a conflict. I found PCN-20210127 note stating this:

#1 Added generic options for PUDC and Boot Mode

Type: Enhancement
Reason: Provide easy option to select pullup/down for CPLD IO pins connected to Zynq Boot Mode and PUDC pins.
Impact: None. Default CPLD source code is still PUDC low (Zynq pullups activated) and Boot Mode QSPI/SD.

So during the startup all the pins of ZynQ have PULLUP enabled. But what happens later before my code starts the main() function (it's bare metal application)? Do the pins stay tristated without PULLUP until I do my system probing and setup SPI directions? The relevant pins are declared as INOUTs my project.

Thank you,
Linas
97
Trenz Electronic FPGA Modules / Re: TEF1002-02 EMC
« Last post by Martin R. on March 14, 2022, 02:10:53 PM »
Good to hear that you found a solution for you.
We will take your recommendation for revision 03 into account.
Thank you!
Martin
98
Trenz Electronic FPGA Modules / Re: TEF1002-02 EMC
« Last post by SteveC on March 13, 2022, 08:02:13 PM »
Hi Martin,

Thanks for your reply.
I have found a good work around, which is to attach an external 5.20V supply across C56 and C57.
This reduces the EMC to zero because the LTM4638 does not supply any current.

I think it would be very useful to bring out the SW (B7 ball) pin to a series resistor and capacitor to 0V, so that a snubber can easily be added.
It would also be useful to bring out the RUN (B4 ball) pin to a pull up resistor, with optional pull down resistor so the LTM4638 can be disabled.

Thanks
Steve Carpenter
99
Hi I'm having trouble implementing a GTH transceiver on a TE0803 SoM. The TE0803 has a Zynq Ultrascale+ ZU4CG on it, and I am using it with the TEBF0808 baseboard.

I have used the GT wizard in vivado to configure the GTH and generate an example design which I have then included in my block design. Initially I am trying to loopback the output serial data into the receiver, I am doing this by wiring the tx outputs of the example design to the rx inputs in the PL.

The design is using MGTREFCLK1 for reference and following the Trenz Starter Kit example and have configured the FSBL to program the SI5338 which drives this reference clock as required, the design is also using the CPLL rather than one of the QPLL. I believe the reference clock is working as I can detect activity on the GTREFCLK_MONITOR_OUT  port of the GTH when I enable it.

However when testing in hardware, when I release the GTH from reset, the CPLL appears to never lock. Though it appears to work fine when I simulate the example design.

I was initially using a reference frequency of 625MHz, I thought perhaps that the clock noise may be too high at this frequency which was causing the issue, however when i change the design and use a 125MHz reference clock is still fails to lock.

I am wondering if there are any required steps that I am missing? Or if anybody has had success with the GTH on the TE0803 and if so, using what frequencies and line rates? Are any steps required to enable the GT power supplies on the TE0803, i.e. MGTAVCC, MGTVCCAUX and MGTAVTT ?

100
Trenz Electronic FPGA Modules / Re: TE0745 Module QSPI Flash not programmable anymore
« Last post by JH on March 10, 2022, 12:06:35 PM »
Hi,
https://support.xilinx.com/s/article/70548?language=en_US
does also not help on all versions of vivado/vivado lab tools.
Here are some notes regarding QSPI programming on different versions:
https://wiki.trenz-electronic.de/pages/viewpage.action?pageId=105689937
br
John
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