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#81
Open source IP / Re: Labtools fmeter
Last post by JH - October 19, 2023, 06:45:56 AM
Hello,
Yes, that is possible. The Fmeter is a simple frequency counter that simply calculates the ratio between known and unknown frequencies.
br
John
#82
Open source IP / Labtools fmeter
Last post by ame - October 18, 2023, 06:18:21 PM
Hello,

I would like to know about the Trenz IP "Labtools fmeter" IP Licence terms.
There is no Licence terms in the source files.
Is it possible to use IP in a commercial project without violating any license terms?

Regards
#83
CYC1000 community projects / Re: Utility to flash FPGA
Last post by lauryfriese - October 18, 2023, 11:13:04 AM
This is so helpful, thanks for the idea.
#84
UltraScale / Re: TE0807 clock wizard lock f...
Last post by JH - October 11, 2023, 06:57:13 AM
Hi,
I must have overlooked your answer. Sorry.
Voltages are actually measured before delivery. It is strange that it was missing. But I'm glad you were able to solve the problem.
br
John
#85
UltraScale / Re: TE0807 clock wizard lock f...
Last post by cs_wiz - October 09, 2023, 04:50:14 AM
Hi,

Yes I am programming the Si5345 in my baremetal code and the power line is also enabled.
As I mentioned in my reply post, this was due to a hardware fault. I managed to get it working after replacing the resistors.

Cheers.
#86
Quote from: JH on October 05, 2023, 09:08:54 AM
Hi,
territorial io
you could simply have the HDL code generated for other device and if it is not encrypted, adjust it to be compatible with Spartan 3. The question is whether it is worth the effort. Spartan 3 is EOL anyway, which means you should develop on newer devices.
br
John
Thanks for your useful advice :)
#87
Trenz Electronic FPGA Modules / Re: TEBF0808 / TE0807 SFP+ Eth...
Last post by JH - October 05, 2023, 12:03:54 PM
QuoteI took the circuit from this post to get the transceiver clock onto normal interconnect and had a look at it with the ILA core and it isn't moving. I don't think a reset issue would do that because the complex ethernet core isn't involved, it's just a couple of buffers
You mean from the other post? Yes, there were only buffers in there. But if you don't connect them properly, you won't see anything.  As far as I can see, he had set the buffers correctly on the other post and then divided CLK down and simply checked whether the counter was working.
The other customer did not comment further on the lack of resistors. We do voltage tests here before delivery, so that should actually be covered.

QuoteIn the end I decided to switch to another board which has multiple RJ45 1G ethernets connected to the PL using RGMII rather than transceivers so I could make progress on the main part of my project.
Ok, I'm sorry I couldn't be of more help. Good luck with your project.

br
John


#88
Trenz Electronic FPGA Modules / Re: TEBF0808 / TE0807 SFP+ Eth...
Last post by tom_kean - October 05, 2023, 11:03:02 AM

Hi John,

I found this post on the forum which describes a similar problem to what I am seeing.

https://forum.trenz-electronic.de/index.php/topic,1775.0.html

I took the circuit from this post to get the transceiver clock onto normal interconnect and had a look at it with the ILA core and it isn't moving. I don't think a reset issue would do that because the complex ethernet core isn't involved, it's just a couple of buffers.  My guess at this point is that either the device tree entry for the clock chip is wrong in some way I don't understand or there is s similar hardware issue to what the person who wrote this post found. The obvious next step would be to probe output 7 from the clock chip with a scope but I am not set up to probe nets on these kind of find pitched surface mount devices.  In the end I decided to switch to another board which has multiple RJ45 1G ethernets connected to the PL using RGMII rather than transceivers so I could make progress on the main part of my project.

#89
Trenz Electronic FPGA Modules / Re: TEBF0808 / TE0807 SFP+ Eth...
Last post by JH - October 05, 2023, 09:14:28 AM
Hi,
Hi, sorry that you have invested so much time so far and it still didn't work out.

The question is, is maybe SI5345 programming over Linux to late. This depends mostly on the protocols and AMD use sometime preliminary configuration inside the FSBL or maybe in your case PL IP reset is maybe released to early?
We add Si5345 runtime programming into our FSBL(see reference design download) before GTR are initialised.  Maybe you can try this also? Alternativle, SI5345 NVM can be programmed via user over I2C, see:
https://wiki.trenz-electronic.de/display/PD/Si5345

If you are lucky this helps, I don't know if it does, but it is at least a possible source of error.

br
John
#90
Trenz Electronic FPGA Modules / Re: TE0320-00ev02IB board work...
Last post by JH - October 05, 2023, 09:08:54 AM
Hi,
you could simply have the HDL code generated for other device and if it is not encrypted, adjust it to be compatible with Spartan 3. The question is whether it is worth the effort. Spartan 3 is EOL anyway, which means you should develop on newer devices.
br
John