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#61

UltraScale / TE820 +TE0706 carrier Ethernet...

Last post by pema - December 05, 2023, 12:27:30 PM

Hi there,
I would like to enable ethernet in u-boot for the TE0820 (connected to gem3).
I added to the .../project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi

Code Select Expand


/*------------------ ETH PHY --------------------*/
&gem3 {
    /delete-property/ local-mac-address;
    phy-handle = <&phy0>;
    nvmem-cells = <&eth0_addr>;
    nvmem-cell-names = "mac-address";
    phy0: phy0@1 {
        device_type = "ethernet-phy";
        reg = <1>;
    };
};


Also tried :

Code Select Expand


&gem3 {
    /delete-property/ local-mac-address;
    phy-handle = <&phy0>;
    nvmem-cells = <&eth0_addr>;
    nvmem-cell-names = "mac-address"
    phy0: phy0@1 {
        device_type = "ethernet-phy";
        reg = <1>;
    };
};


As provided in the BSP for the TE0820. But this gives me an error during compilation.
is there any thing else that needs to be added to the kernel config or u-boot config?

The error output are little enigmatic for me:

Code Select Expand


| during RTL pass: cse2
| /home/ubuntu/dev_petalinux/xr23_rtfg/build/tmp/work-shared/zynqmp-generic-xczu3cg/kernel-source/fs/btrfs/extent_io.c: In function 'btree_write_cache_pages':
| /home/ubuntu/dev_petalinux/xr23_rtfg/build/tmp/work-shared/zynqmp-generic-xczu3cg/kernel-source/fs/btrfs/extent_io.c:3074:1: internal compiler error: in validate_canon_reg, at cse.cc:2804
|  3074 | }
|       | ^
| 0x183eec9 internal_error(char const*, ...)
| ???:0
| 0x6a8cf6 fancy_abort(char const*, int, char const*)
| ???:0
| Please submit a full bug report, with preprocessed source (by using -freport-bug).
| Please include the complete backtrace with any bug report.
| See <https://gcc.gnu.org/bugs/> for instructions.
| make[3]: *** [/home/ubuntu/dev_petalinux/xr23_rtfg/build/tmp/work-shared/zynqmp-generic-xczu3cg/kernel-source/scripts/Makefile.build:250: fs/btrfs/extent_io.o] Error 1
| make[3]: *** Waiting for unfinished jobs....
|   CC      fs/proc_namespace.o
|   CC      fs/eventpoll.o
|   CC      fs/anon_inodes.o
|   CC      fs/signalfd.o
|   CC      fs/timerfd.o
|   CC      fs/eventfd.o
|   CC      fs/aio.o
|   CC      fs/locks.o
|   CC      fs/binfmt_script.o
|   CC      fs/binfmt_elf.o
|   CC      fs/compat_binfmt_elf.o
| make[2]: *** [/home/ubuntu/dev_petalinux/xr23_rtfg/build/tmp/work-shared/zynqmp-generic-xczu3cg/kernel-source/scripts/Makefile.build:500: fs/btrfs] Error 2
| make[2]: *** Waiting for unfinished jobs....
| make[1]: *** [/home/ubuntu/dev_petalinux/xr23_rtfg/build/tmp/work-shared/zynqmp-generic-xczu3cg/kernel-source/scripts/Makefile.build:500: fs] Error 2
| make: *** [/home/ubuntu/dev_petalinux/xr23_rtfg/build/tmp/work-shared/zynqmp-generic-xczu3cg/kernel-source/Makefile:1992: .] Error 2
| ERROR: oe_runmake failed
| WARNING: /home/ubuntu/dev_petalinux/xr23_rtfg/build/tmp/work/zynqmp_generic_xczu3cg-xilinx-linux/linux-xlnx/6.1.5-xilinx-v2023.1+gitAUTOINC+716921b6d7-r0/temp/run.do_compile.792878:307 exit 1 from 'exit 1'
| WARNING: Backtrace (BB generated script):
| #1: bbfatal_log, /home/ubuntu/dev_petalinux/xr23_rtfg/build/tmp/work/zynqmp_generic_xczu3cg-xilinx-linux/linux-xlnx/6.1.5-xilinx-v2023.1+gitAUTOINC+716921b6d7-r0/temp/run.do_compile.792878, line 307
| #2: die, /home/ubuntu/dev_petalinux/xr23_rtfg/build/tmp/work/zynqmp_generic_xczu3cg-xilinx-linux/linux-xlnx/6.1.5-xilinx-v2023.1+gitAUTOINC+716921b6d7-r0/temp/run.do_compile.792878, line 291
| #3: oe_runmake, /home/ubuntu/dev_petalinux/xr23_rtfg/build/tmp/work/zynqmp_generic_xczu3cg-xilinx-linux/linux-xlnx/6.1.5-xilinx-v2023.1+gitAUTOINC+716921b6d7-r0/temp/run.do_compile.792878, line 219
| #4: kernel_do_compile, /home/ubuntu/dev_petalinux/xr23_rtfg/build/tmp/work/zynqmp_generic_xczu3cg-xilinx-linux/linux-xlnx/6.1.5-xilinx-v2023.1+gitAUTOINC+716921b6d7-r0/temp/run.do_compile.792878, line 203
| #5: do_compile, /home/ubuntu/dev_petalinux/xr23_rtfg/build/tmp/work/zynqmp_generic_xczu3cg-xilinx-linux/linux-xlnx/6.1.5-xilinx-v2023.1+gitAUTOINC+716921b6d7-r0/temp/run.do_compile.792878, line 149
| #6: main, /home/ubuntu/dev_petalinux/xr23_rtfg/build/tmp/work/zynqmp_generic_xczu3cg-xilinx-linux/linux-xlnx/6.1.5-xilinx-v2023.1+gitAUTOINC+716921b6d7-r0/temp/run.do_compile.792878, line 311
ERROR: Task (/home/ubuntu/dev_petalinux/xr23_rtfg/components/yocto/layers/meta-xilinx/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2023.1.bb:do_compile) failed with exit code '1'
NOTE: Tasks Summary: Attempted 4158 tasks of which 3816 didn't need to be rerun and 2 failed.


any help would be appreciated. Kinda stuck and I just need this to speed up my development tryouts.
Many Thanks

#62

UltraScale / Re: Reference Design & Custom ...

Last post by JH - December 04, 2023, 07:27:45 AM

Hi,
see schematics page 26 (U5 SI5345), page 18 (GTR), page14,15 (GTH):
https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0818/REV01/Documents

GTR configuration(used interfaces, PCIe, SATA,USB3, DP....) depends on the carrier.
For TEBF0818 carrier, we offer reference designs with basic configuration:
https://wiki.trenz-electronic.de/display/PD/TE0818+StarterKit
br
John

#63

Trenz Electronic FPGA Modules / Re: TE0720 D5 LED behavior?

Last post by JH - December 04, 2023, 07:22:46 AM

Hi,
TE0720 CPLD Description is here:
https://wiki.trenz-electronic.de/display/PD/TE0720+CPLD#TE0720CPLD-On-boardLEDs
What's the status of the other 2 LEDs?

There is normally some problem in case it blinks.
If everything starts up correctly. LED5 can be controlled from user via MDIO interface, see:
https://wiki.trenz-electronic.de/display/PD/TE0720+CPLD#TE0720CPLD-SCMDIOInterface
Examples to get access are included into the documentation or our reference designs:
https://wiki.trenz-electronic.de/display/PD/TE0720+CPLD#TE0720CPLD-CRregistersaccessmethods

br
John

#64

Trenz Electronic FPGA Modules / Re: TEBF0808's SI5338 configur...

Last post by nickleassa - November 30, 2023, 02:56:38 AM

thanks John

#65

Trenz Electronic FPGA Modules / TE0720 D5 LED behavior?

Last post by AaronB - November 29, 2023, 05:43:50 PM

I am currently booting petalinux using a TE0720 mounted on a custom board.  In my boot image, I have a firmware image that should be getting flashed by the first stage boot loader.  Everything seems like its working, so maybe this is a request for information.

Can someone tell me if this D5 LED is supposed to continue blinking forever?  This is what I am seeing, but for some reason, I thought it was supposed to stop blinking once the firmware was programmed.  I'm poking around in petalinux, and it looks like my firmware might be loaded.  However, I wonder if I did everything correctly.

the TRM only says this LED is controlled by the System Controller CPLD, without reference to its expected behavior.  I understand through experience and forum posts that it blinks quickly for QSPI boot and slowly for SD boot.  There are also forum references to 1/8 duty cycle blinking in some cases, though I don't think I've ever seen this.

I have seen forum links to a wiki page on trenz's website, but I don't appear to have access to that.  I get an Atlassian login page that doesn't appear to accept my credientials for forum.trenz-electronic.de.

#66

CYC1000 community projects / Re: I present a comunity of IN...

Last post by Subcritical - November 26, 2023, 05:12:49 PM

There are also a Minimig core in development, That suports AGA and uses the UnAMIGA branch.

https://youtu.be/8tbrBpbKonQ?si=m3qmASQROg6OqNrN

#67

CYC1000 community projects / Re: I present a comunity of IN...

Last post by Subcritical - November 24, 2023, 01:58:35 PM

This is an interactive bill of materials, nowadays the SD has 4bit mode and is not share with the 2x20 Raspberry pi port. But in the future i'm going to share the signals an put also in the 2x20 pi bus.
Nowadays also seeing the rp2040, to control the cores that were sintetized in the platform.



More info available here:
https://github.com/AtlasFPGA/CYC1000

#68

Trenz Electronic FPGA Modules / Re: TE0705 USB over-current si...

Last post by JH - November 24, 2023, 12:37:54 PM

Hi, you can only read it over I2C IP:
https://wiki.trenz-electronic.de/display/PD/TE0705+CPLD#TE0705CPLD-I2CtoGPIOregisters

CPLD Source code is available on the download area of the TE0705, so you can change it like you want.
br
John

#69

UltraScale / Re: TE0820 POR with JTAG TE079...

Last post by pema - November 24, 2023, 11:21:18 AM

Ok I got it. now. Thanks for clearing that up. 

#70

UltraScale / Re: TE0820 POR with JTAG TE079...

Last post by JH - November 24, 2023, 10:42:09 AM

Hi,
Button goes directly to the 2.54 mm pinheader(so output from XMOD):
https://wiki.trenz-electronic.de/display/PD/TE0790+TRM#TE0790TRM-BlockDiagram
and to this pin(Input for CPLD). It simple xor LED so you can see that you press the button
https://wiki.trenz-electronic.de/display/PD/TE0790+CPLD+-+XMOD+Standard#TE0790CPLDXMODStandard-LED

Or see schematics and source code.

In case you didn't press button, than you can also use G as output or set G as tri state with pullup activated where you force only to GND, in this case you didn't get a electrical conflict when someone press the button.


br
John