Recent Posts

Pages: 1 2 [3] 4 5 ... 10
21
Trenz Electronic FPGA Modules / TE0713 FT600 USB3 IC
« Last post by hopi on May 08, 2022, 02:51:05 PM »
Hallo,

kann ich den FT600 chip resetten durch den FPGA ? Ich sehe im Schaltplan die Verbindung genannt FPGA0_IO1. Oder gibt es eine andere Moeglichkeit ?

Mit freundlichen Gruessen

Pierre
22
Trenz Electronic FPGA Modules / TE-0720 EUI-48/64 Unique ID
« Last post by bigguiness on May 07, 2022, 12:40:02 AM »
Hello,

Is it possible to read the EUI-48/64 Unique ID on a TE-0720 board from Linux?

What is the size of the Unique ID?

Thanks
23
Hi,
theoretical it works without PS, but SI5338 is not programmed by default this will done by our FSBL during booting.
So in any case you need PS.
But it's much easier to use PS-PL CLKs (you can modify PS IP). In this case it's also important to regenerate FSBL, because FSBL configures PS with configuration from XSA export. Bitstream is PL only.

Regarding your "Error" when you add the attribute(CLOCK_DEDICATED_ROUTE) which Xilinx mentions there than it's possible to generate bitstream. Problem is that you use a Port which is not recommended to use for CLK --> CLK signal must routed over fabric into the CLK network of the FPGA, which is problematic for timing calculation (but manly when you use the same CLK also on external devices...).

br
John
24
Hello everyone,
Thanks in advance for your help.

I am new to hardware world and using TE0820.

The reference design works perfect on my board. The block design looks like this:


I can remove SI5338 parts and use PS as clock source like this:


My question is: is that possible using SI5338 or other clock on the board as the clock source for my design? What I want to do is like this:

Or something like this:


I tried, failed and got an error like this:
Quote
[Place 30-675] Sub-optimal placement for a global clock-capable IO pin and BUFG pair.If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
   < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets design_1_i/util_ds_buf_0/U0/USE_IBUFDS.GEN_IBUFDS[0].IBUFDS_I/O] >

   design_1_i/util_ds_buf_0/U0/USE_IBUFDS.GEN_IBUFDS[0].IBUFDS_I/IBUFCTRL_INST (IBUFCTRL.O) is locked to IOB_X2Y99
    design_1_i/util_ds_buf_0/U0/IBUF_OUT[0]_BUFG_inst (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y1

   The above error could possibly be related to other connected instances. Following is a list of
   all the related clock rules and their respective instances.

   Clock Rule: rule_bufgce_bufg_conflict
   Status: PASS
   Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
   used at the same time
    and design_1_i/util_ds_buf_0/U0/IBUF_OUT[0]_BUFG_inst (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y1
I am not sure what it means.


25
Trenz Electronic FPGA Modules / Re: TE0725-03-100-2I9 in field programming
« Last post by qojote on May 04, 2022, 09:06:47 AM »
Hi,
Thanks for your support. In fact your link is helpful, especially the article about limitations. The reference design file including the "SpiFlashProgrammer" module can be downloaded here: https://docs.xilinx.com/v/u/en-US/xapp1081-quickboot-remote-update. There is a table in the corresponding AN pdf named "Table 11: SpiFlashProgrammer.vhd Parameters" where the parameters which need to be configured are described. Besides that only "cMicronN25Q" is supported i need information about the "SPI flash device Device ID from RDID", the SPI sector size, the SPI page size and so on.
Flashing via the Xilinx tools and JTAG does work perfectly for me but this is no option in the field. The bistream is not too big which means i do not need high speed transfer. I am planing to write portions of the bitfile into the FPGA (registers or BRAM) and let the "SpiFlashProgrammer" erase and refill the correct portion of the flash so that the next reboot will jump into the new program.
BR
26
Hi,
maybe it's easier to change TE0701 CPLD --> remove CD Pin from Boot mode selection and set constant to QSPI.
Source code and update instructions:
https://wiki.trenz-electronic.de/display/PD/TE0701+CPLD+Firmware
And keep SD inside after power on

Linux SD reinitialization should also be possible, but I can't tell you off the top of my head how you do this.

br
John
27
UltraScale / Re: TE0841 flash and DDR4
« Last post by JH on May 04, 2022, 08:01:37 AM »
Hi,
can you tell me which datasheet you has used?
k4a8g165wb-birc is  8Gbit:
https://semiconductor.samsung.com/dram/ddr/ddr4/k4a8g165wb-birc/

And yes row address is wrong, should be 16 (but it works also with 15). We will change to 16 for 2021.2 release, which is in preparation at the moment. Thank you for pointing out this mistake.

br
John
28
Hi,
Quote
1) For the SD0 eMMC entry, I see:
              // disable-wp
    which implies that the write protect is not disabled - However I am able to format and wrote to the eMMC device.
    How is this possible?
That's a question to xilinx :-)
Maybe this will be ignored. Did you translate final dtb back dts and check if it was add there?
Quote
2) The SD0 eMMC entry also shows:
            no-1-8-v
    Again, this implies that the eMMC should be running at 3.3V. However, when I look at the schematic, I see it is connected to Bank 500 which is a 1.8V bank
    Also - the SDINBDG4-8G NAND chip uses 1.8V for VCCQ
    I would like to understand why the SD0 eMMC entry is set for no-1-8-v?
In the past some customer has detected sometime linux access problem and this property has solved this(I don't know why)....maybe it's not longer needed.
Quote
The SD1 sd2.0 entry shows no-1-8-v, which makes sense, since this SDIO bus is on BANK 501 and 3.3V
    However, the TE0701 uses a voltage translator U2 from 1.8v to 3.3v running from VIOB which is 1.8v on JM1
    I don't understand how the voltage translator could be working? i.e. the FPGA side will be getting 1.8v from the translator?
See note:https://wiki.trenz-electronic.de/display/PD/4+x+5+SoM+Carriers#id-4x5SoMCarriers-TE0701
TE0701 was original design for our 7 series Zynq module which use 1.8V. On the next PCB update it's planned to add jumper for voltage selection...
br
John
 
29
Trenz Electronic FPGA Modules / Re: TE0725-03-100-2I9 in field programming
« Last post by JH on May 04, 2022, 07:05:58 AM »
Hi,
I don't know "VHD SpiFlashProgrammer module", so I can't help much. Here is some link which I found, maybe it helps you:
https://support.xilinx.com/s/article/69824?language=en_US

We use Vivado to transfer data to flash or linux(is not possible on TE0725) later to get access. Flash on the TE0725 is supported by Xilinx and Xilinx default QSPI IP. it's strange that it should be no supported by this xilinx tool, but sometimes this can happens (or it's only not in some list, maybe you try out).

but in any case you must transfer data from somewhere to the FPGA BRAM, and on TE0725 you has only JTAG, UART or other low speed interfaces(I2C,SPI...) available...

br
John
30
Hello Everyone,

I have been working with the test_board reference design for the TE0820 for a few weeks now
Using Vivado 2021.2 and Petalinux 2021.2

Ran into a couple questions about the system device tree in "system-user.dtsi"

1) For the SD0 eMMC entry, I see:
              // disable-wp
    which implies that the write protect is not disabled - However I am able to format and wrote to the eMMC device.
    How is this possible?

2) The SD0 eMMC entry also shows:
            no-1-8-v
    Again, this implies that the eMMC should be running at 3.3V. However, when I look at the schematic, I see it is connected to Bank 500 which is a 1.8V bank
    Also - the SDINBDG4-8G NAND chip uses 1.8V for VCCQ
    I would like to understand why the SD0 eMMC entry is set for no-1-8-v?

3) The SD1 sd2.0 entry shows no-1-8-v, which makes sense, since this SDIO bus is on BANK 501 and 3.3V
    However, the TE0701 uses a voltage translator U2 from 1.8v to 3.3v running from VIOB which is 1.8v on JM1
    I don't understand how the voltage translator could be working? i.e. the FPGA side will be getting 1.8v from the translator?

Thank you for your help.
Dave
Pages: 1 2 [3] 4 5 ... 10