TE0783 (Lattice CPLD firmware)

[andrew712]

Hi, I'm trying to understand how the RGPIO ports TE0783  are connected, I watched the RPIO description for CLPD, I understand how groups 19 ... 0 are used (connected to EXTIO), 24 ... 27 reserve is not used, 28 ... 31 activation code " 1010 ", but I don't understand these RGPIO contacts (Connected to RGPIO 20 ... 23), and these contacts go in both directions (cpld from fpga) and (cpld to fpga)?

[JH]

Hi,
RGPIO are included into our Reference Design and can be controlled via Vivado HW-Manager over VIO debug core:
https://wiki.trenz-electronic.de/display/PD/TE0783+Test+Board#TE0783TestBoard-VivadoHWManager

RGPIO IP has 32 input and 32 output IOs, they will be translate to a serial lines (2 date and 1 clk) and on CPLD back to 32input and 32 output signals.
First 20 bits control external IO (Even number are outputs, odd inputs from RGPIO on FPGA). next 4 are simple loopbacked ( you reserve what you set), 4 bits are reserved and the last 4 bits are used to actives the core--> Data will only transmitted when your set the last 4 bits to 1010.

br
John