Author Topic: pll constarints  (Read 557 times)

Manuel

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pll constarints
« on: August 23, 2021, 07:59:47 AM »
Dear all,
I started to make a design on the TE0808-5 with the TRBF0808 Carrier Board.
I want to use the PS clock to generate several clocks for the PL. In the picture you could see how it is connected.

PS clocks:
pl_clk1 is 25MHz
pl_clk0 is 100MHz

PLL connection:
clk_out1 is 100MHz
clk_out2 is 50MHz
clk_out3 is 20MHz
clk_out4 is 10MHz

My constraints looks as follows:
create_clock -period 40.000 -name clk_in1 [get_ports clk_in1]

After implementation I got several inter-clock path errors.

Any suggestion or hints how to solve the problem? Do I have to introduce more constraints or buffering?

JH

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Re: pll constarints
« Reply #1 on: August 25, 2021, 07:01:54 AM »
Hi,
from which pin comes your clk_in1 ?
br
John

Manuel

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Re: pll constarints
« Reply #2 on: August 25, 2021, 07:22:32 AM »
From the pl_clk1 of the Zynq.

JH

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Re: pll constarints
« Reply #3 on: August 25, 2021, 08:38:58 AM »
additional clk constrain is normally not need in this case, this will be generated automatically.
Can you tell me exact error message, when you try to generate the files? Or send me the log file
Which Vivado version did you use?
...
Quick addition: Could it be that I have misunderstood you? Building is possible but you only get timing errors? from clk crossing?


br
John
« Last Edit: August 25, 2021, 08:40:44 AM by JH »

Manuel

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Re: pll constarints
« Reply #4 on: August 25, 2021, 08:59:15 AM »
With your comment of the automated generated constraints of the pll I thought it is a problem in my design.
So I simplified my clock distribution, and removed the additional pll constraints cause they are generated automatically. Now it is building the project.

Many thanks
Manuel

JH

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Re: pll constarints
« Reply #5 on: August 25, 2021, 09:09:58 AM »
Hi,
some additional note:
1. You has different AXI master IPs on your interconnect and you has connect all to the same clk? This IPs have the same clk? You must use AXI CLK which is also used on each IP there. CLk crossing will be done by interconnect IO.
2. PS-PL CLKs will be initialised via FSBL, bitstream itself will not enable CLKs...

br
John

Manuel

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Re: pll constarints
« Reply #6 on: August 25, 2021, 09:27:27 AM »
With the simplification of my clock distribution, I guess I solved AXI clock problematic you mentioned.

About the number two and the PS-PL CLKs, I thought with the TEBF0808 I have no other chance. Cause there is no external oscillator connected to the te0808-5 to use directly in the PL part. Did I understand this correct?

JH

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Re: pll constarints
« Reply #7 on: August 25, 2021, 11:52:40 AM »
Quote
About the number two and the PS-PL CLKs, I thought with the TEBF0808 I have no other chance. Cause there is no external oscillator connected to the te0808-5 to use directly in the PL part. Did I understand this correct?
This one only a information, sometimes customer program only PL and didn't get any PS-PL CLK...

TE0808 has also external PLL(SI5345), this PLL is not programmed, on our example this will be done on runtime with FSBL(code is included). You can also use some of this CLKs (routing from MGT ref to fabric is possible with correct Xilinx IP). PLL has also NVM which can be programmed.

Or use FMC Card which provides CLKs...


But in your case I think PS-PL CLK is better and easer choice.
br
John