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Trenz Electronic GmbH Support Forum

Trenz Electronic Products => Trenz Electronic FPGA Modules => Topic started by: bparmeter on April 19, 2016, 09:58:09 PM

Title: TE0720-2 startup pin state
Post by: bparmeter on April 19, 2016, 09:58:09 PM
During power up I would like for the pins to be held in a low state. To do this PUDC_B needs to be pulled high. Currently PUDC_B appears to be pulled low, so the outputs are all high during power up.

According to the TE0720-2IF schematics, PUDC_B appears to be directly tied to the CPLD. Is there a way to reprogram the SC so that this pin is pulled high?
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