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Trenz Electronic Products => Trenz Electronic FPGA Modules => Topic started by: maria on March 08, 2016, 05:04:14 PM

Title: TE0712 reference design for vivado 2015.4 with Ethernet and DDR
Post by: maria on March 08, 2016, 05:04:14 PM
Hi,
Is there a reference design for TE0712 for 2015.4 similar to the one illustrated in Wiki section for vivado 2014.3 (interface connection between Processor and peripherals).
I would like to test peripherals with TE703 board (Ethernet, DDR) and It will be very helpful to have an example design with correct connections and constraints to start.
Thanks.
Title: Re: TE0712 reference design for vivado 2015.4 with Ethernet and DDR
Post by: Antti Lukats on March 09, 2016, 11:14:06 AM
is in preparation, all modules get 2015.4 ref design done.
Title: Re: TE0712 reference design for vivado 2015.4 with Ethernet and DDR
Post by: JH on March 10, 2016, 10:23:57 AM
Hi,

now, you can find a new reference design on the Trenz Electronic website:
http://www.trenz-electronic.de/de/download/d0/Trenz_Electronic/d1/TE0712/d2/reference_designs/d3/2015.4/d4/test_board.html

Some additional information:
https://wiki.trenz-electronic.de/display/PD/Project+Delivery

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Title: Re: TE0712 reference design for vivado 2015.4 with Ethernet and DDR
Post by: maria on March 11, 2016, 02:59:22 PM
Thank you, it is really helpful but I have some questions about the design.

First, I don't understand to what is connected the UART interface on the TE7012 board. Is it mapped to board connectors to be connected through a base board? and to what (I'm using the TE0703)?

I have another question about the ethernet clocking, there is a mismatch between Xilinx specifications and the design.t According to Xilinx Product Guide the MII to RMII ip and the Ethernet PHY should be clocked with the same clock to 50Mhz. I guess the Ethernet PHY on the board is clocked to 50Mhz but in the design the MII to RMII ip is clocked to 100Mhz. Is it normal?

Thanks.
Title: Re: TE0712 reference design for vivado 2015.4 with Ethernet and DDR
Post by: Antti Lukats on March 11, 2016, 04:30:08 PM
TE0712 is kept as much as possible backward compatible to TE0720, where we had default UART pins (controlled by the CPU in zynq).

Those pins are by default used as UART on the baseboards, like TE0703

but on TE0712 all FPGA can be user defined, so if not needed those pins can be used for other purpose
Title: Re: TE0712 reference design for vivado 2015.4 with Ethernet and DDR
Post by: GuinnessTrinker on April 01, 2016, 07:46:39 AM
Quote from: JH on March 10, 2016, 10:23:57 AM
now, you can find a new reference design on the Trenz Electronic website:
http://www.trenz-electronic.de/de/download/d0/Trenz_Electronic/d1/TE0712/d2/reference_designs/d3/2015.4/d4/test_board.html

Sorry, but this is an endless recursion:

http://www.trenz-electronic.de/de/download/d0/Trenz_Electronic/d1/TE0720-GigaZee/d2/Reference%20Designs/d3/2015.4/d4/test_board.html

is pointing to

-> GitHub
-> TE0720-GigaZee-Reference-Designs
https://github.com/Trenz-Electronic/TE0720-GigaZee-Reference-Designs

"Notice: This archive is obsolete, please use only latest desings available under
http://www.trenz-electronic.de/de/download/d0/Trenz_Electronic/d1/TE0720-GigaZee.html
This repository will be deleted in future!"

So it starts from beginning ;-)

Title: Re: TE0712 reference design for vivado 2015.4 with Ethernet and DDR
Post by: Antti Lukats on April 01, 2016, 05:27:08 PM
you are asking about TE0720 in the thread "TE0712" ? those are different products. One is zynq one is artix based
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