Hi,
Using the test_board example Vivado design, I've taken the steps necessary to utilize the gigabit ethernet interface that is connected to the RJ45 port on the baseboard. After reading the schematic, I enabled GEM3 on MIO pins 64-75 (see attached images).
I started with the TCP Echo Server (FreeRTOS + lwIP) example software project in Vitis. The software runs, but I cannot connect to the server at all. I've narrowed it down to usage of vTaskDelay() in the application. It appears that the scheduler context switches to the idle task and gets stuck there. This suggests timer tick interrupts are not handled properly. Has anyone experienced this issue before?
Thanks for your help!
Hi,
we use only linux for ETH. So I can't help much for IwIP core. --> If I remember correctly you must also activate Timer in PS IP (we do this default with our board files). Maybe this helps.
For IwIP itself it's maybe better to write also on Xilinx forum, it's more general issue and Xilinx community is bigger
br
John
JH,
Thanks for the suggestion. I've verified that all four TTC modules are enabled in the Zynq configuration.
What solved my issue was to use the FreeRTOS Hello World example and enable lwIP in the BSP settings. Then I copied my test code into that project and the issues were no longer present. Not sure what exactly was happening behind the scenes though.