Trenz Electronic GmbH Support Forum

Trenz Electronic Products => Trenz Electronic FPGA Modules => Topic started by: Gloria on May 25, 2021, 10:23:56 AM

Title: zynqberry1 demo of TE0726
Post by: Gloria on May 25, 2021, 10:23:56 AM
Hi,
There is a axi4 mipi_ppi to axis ip in the demo. Does the data format of mipi_ppi is RAW10? or RAW8?
Through the ip <mipi_ppi to axis>, I notice that the axis data width is 16, what pixels of the 16 bit data includes ?
Or is there the reference document about above question?
Thank you!
Title: Re: zynqberry1 demo of TE0726
Post by: Oleksandr Kiyenko on May 25, 2021, 10:42:45 AM
Hi Gloria,
the format is RAW10.
You can check the datasheet for the sensor of your camera module.

Best regards
Oleksandr Kiyenko
Title: Re: zynqberry1 demo of TE0726
Post by: Gloria on May 25, 2021, 01:28:04 PM
Thank you,
there is another question,
Through the ip <mipi_ppi to axis>, I notice that the axis data width is 16, what pixels of the 16 bit data includes ?Is it one 16-bit axis data include one pixel?
Or is there the reference document about above question?
For example, in xilinx csi2-rx user guide, when raw10 is transferred to axis,the data width is 64
Title: Re: zynqberry1 demo of TE0726
Post by: Oleksandr Kiyenko on May 26, 2021, 07:56:48 AM
Hi Gloria,

this example is my own implementation of the CSI interface, it was made a long time ago before the MIPI CSI core from Xilinx become available.
In video datapath, blocks before the demosaic operation are operating with raw data format which for this case is 2 lane*8 bits so we have a 16-bit interface.
Now you can use the core from Xilinx, as I know you can request a limited license for free. I didn't check it, but sure that it's implemented in the more correct way and
have good documentation.


Best regards
Oleksandr Kiyenko