I want to use P2 with SPI. four of the signals (EX_IO1 - EX_IO4) go to the CPLD. Are they routed to any pins from the FPGA, for example MIO26-MIO29 (that would be ideal)?
Hi,
EX_IO1 - EX_IO4 are not used in the CPLD:
https://wiki.trenz-electronic.de/display/PD/TEBF0808+CPLD
CPLD source code is available on the download area, in case you want to modify-
br
John