Recent posts

#91

Trenz Electronic FPGA Modules / Re: FSBL hangs when initializi...

Last post by Waldi3141 - June 18, 2024, 04:07:03 PM

Hello Stonebull,

can you try our latest 2022.2 reference design?
https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0715/Reference_Design/2022.2/test_board

I just flashed the hello_te0715 BOOT.bin file to the onboard qspi flash and it boots and programs the PLL just normal on the TE0701. You can use the prebuilt file from our 2022.2 project and try it out without rebuilding anything.

Also, you might need to update the TE0715 CPLD firmware
https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0715

best regards
waldi

#92

Trenz Electronic FPGA Modules / TEM0009 module

Last post by midlandsscud - June 14, 2024, 06:30:11 AM

Can you please provide a .stp file for the TEM0009 module?

#93

Trenz Electronic FPGA Modules / FSBL hangs when initializing S...

Last post by Stonebull - June 13, 2024, 09:37:56 PM

Hello,
I am using a TE0715 together with the TE0701 carrier board with Vivado 2019.1. I started my project based on the supplied reference project from trenz for the specific board.

I am having problems getting any program to boot from flash lately and I just cannot figure out what's wrong. I run bare-metal software on the ARM cortex A9.
For simplicity I tried with the simple trenz_hello_world project, which I successfully flashed onto the SoM, but during boot the FSBL(trenz modified) hangs with the following output:

Code Select Expand

--------------------------------------------------------------------------------<\r>
<\n>
Xilinx First Stage Boot Loader (TE modified)
<\n>
<\r>Release 2018.3<9>Jun 13 2024-15:58:55<\r>
<\n>
<\r>
<\n>
Device IDCODE: 373B093<\r>
<\n>
Device Name: 7z015 (1B)<\r>
<\n>
Device Revision: 0 <\r>
<\n>
--------------------------------------------------------------------------------<\r>
<\n>
TE0715 TE_FsblHookBeforeHandoff_Custom<\r>
<\n>
Configure TE715 SI5338<\r>
<\n>
Si5338 Init Registers Write.<\r>
<\n>
Si5338 Hard reset done.<\r>
<\n>

I left all FSBL(trenz_modified) files untoutched except for enabling the DEBUG_INFO switch and adding a few more p_print() for more info about when the fsbl fails.

Code Select Expand

int si5338_init(unsigned char chip_addr)
{
int i;
u8 reg_val;
Reg_Data rd;
int Status;

    //p_printf(("Si5338 Init Start.\r\n"));
    //iic_init();
    p_printf(("Si5338 Init Registers Write.\r\n"));

// I2C Programming Procedure
iic_write8( chip_addr, 246, 0x01); //Hard reset
p_printf(("Si5338 Hard reset done.\r\n"));

// Disable Outputs
iic_write8_mask( chip_addr, 230, EOB_ALL, EOB_ALL); // EOB_ALL = 1
p_printf(("Si5338 Disable Outputs done.\r\n"));

// Pause LOL
iic_write8_mask( chip_addr, 241, DIS_LOL, DIS_LOL); // DIS_LOL = 1
p_printf(("Si5338 Pause LOL done.\r\n"));

        ...

Judging from the output I'd say that the fsbl is not able to communicate with the clock generator.

Maybe it is worth mentioning that I've removed and later re-added the I2C1 from the design.
I noticed too late that the I2C1 resource is actually used during boot, but as I re-added it to the MIO pins 48/49 like it was before, I guess that should not be the problem now.

Does anybody have any ideas on how to proceed?
Any help is appreciated.

#94

Trenz Electronic FPGA Modules / How to turn the FT2232H to the...

Last post by flammmable - May 31, 2024, 05:07:59 PM

There is a topic where tells how to config a 93C56 memory attached to the FT4232 chip in the FlashPro5 programmer.


I have a FT2232 board and I config this as topic tells. My board recognized by the FPExpress as a FlashPro5 programmer. But the Ping command runs with an error:
"warpFtdi_FT_OpenEx - Port D".


The FT4232H chip has four ports and the FT2232 has only two ports. Obviously the FPExpress try to use the PORT D that the FT2232 does not have.

But your TEM0001 devboard use the FT2232 chip with PORT A!

So, how to config the FT2232 to turn it to the FlashPro5?

#95

Trenz Electronic FPGA Modules / Re: TE0715 QSPI boot not worki...

Last post by JH - May 31, 2024, 08:47:28 AM

Good to hear that it works know.
Some note regarding PGOOD: This is a multifunction pin and used also as addition boot mode Pin now. (PGOOD output and as boot Mode input) to allow JTAG only boot mode, which is necessary for newer Vivado Versions to programm QSPI Flash, see:

• https://wiki.trenz-electronic.de/display/PD/TE0715+CPLD#TE0715CPLD-BootMode
•     CPLD description
• https://wiki.trenz-electronic.de/display/PD/4+x+5+SoM+Integration+Guide#id-4x5SoMIntegrationGuide-4x5ModuleControllerIOs
•     general notes to the controller signals
• https://wiki.trenz-electronic.de/pages/viewpage.action?pageId=105689937
•     general notes to QSPI programming

br
John

#96

Trenz Electronic FPGA Modules / Re: TE0715 QSPI boot not worki...

Last post by zhjaafri - May 30, 2024, 03:03:06 PM

Thanks alot for your reply, I had populated LED indicator at PGood pin on carrier board which was causing voltage drop on the pin. We removed this connection and now som is booting normally.
Yes, I also wrote to technical support and thanks for their help too.
Regards

#97

Trenz Electronic FPGA Modules / Re: TE0715 QSPI boot not worki...

Last post by JH - May 28, 2024, 01:38:25 PM

Hi,
Mode Pin controls Boot mode and when you has it floating, I would expect QSPI boot Mode, because CPLD of TE0715 has week pullup activated. This should be OK normally, but it's not good to keep this floating.

Can you tell me how you connect all these controller pins on your carrier?
https://wiki.trenz-electronic.de/display/PD/4+x+5+SoM+Integration+Guide#id-4x5SoMIntegrationGuide-4x5ModuleControllerIOs

Can you tell me the LEDs when your appr. the module(firmware and some LED status signal has changed last year):
https://wiki.trenz-electronic.de/display/PD/TE0715+TRM#TE0715TRM-MainComponents
https://wiki.trenz-electronic.de/display/PD/TE0715+CPLD

PS: Did you write also to the technical support?
br
John

#98

UltraScale / Re: TEF1002-02 with TE0820-05

Last post by harrx - May 28, 2024, 01:27:55 PM

Hi Martin,

Yes thanks this worked. I had the same jumper positions, but somwhow switching them off and on again after connecting the JTAG makes the connection.

[jtagen]

#99

Trenz Electronic FPGA Modules / TE0715 QSPI boot not working

Last post by zhjaafri - May 28, 2024, 04:28:13 AM

I am using TE0715 module with our own designed carrier as per connections of TE0706. We have developed a program which works fine on both TE0706 and our developed pcb when programmed using jtag. But when we try to boot using qspi flash it works fine on TE0706 Board but does not works on our pcb. Although we have applied same settings for jtagen and mode pins for som. jtagen pin is set to gnd where as mode pin is left open and en1 pin is pulled up using 10k resistor.
suggest me solution for this problem.

#100

UltraScale / Re: TEF1002-02 with TE0820-05

Last post by Martin R. - May 27, 2024, 10:32:15 AM

Hi,

there are three dips (S2-4, S2-5, S2-6) associated with JTAG, they should all be in off position for JTAG access to SoC of TE0820.
https://wiki.trenz-electronic.de/display/PD/TEF1002+SC+CPLD+MAX10#TEF1002SCCPLDMAX10-JTAGMUX

There is one further dip which enables the module (S2-7) this should be in ON position. See https://wiki.trenz-electronic.de/display/PD/TEF1002+Getting+Started#TEF1002GettingStarted-DIP-SwitchesandPushButtons
If this is not on also D4 on carrier should blink https://wiki.trenz-electronic.de/display/PD/TEF1002+SC+CPLD+MAX10#TEF1002SCCPLDMAX10-StatusLED

Do you see 'unknown device' in vivado if switching to carrier cpld JTAG or module cpld JTAG?

The green LEDS on TEF1002 are D3 and D4? They should be constant on.

What do you mean by xilinx programmer method? You connected  programmer with fly-wires to J5?
J19 PJTAG is different and has to be enabled in the design.

did you try to just boot our pre-build reference design from SD card? Do you see anything on UART output?