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1
Trenz Electronic FPGA Modules / Re: LVDS with TE0711 mounted on TE0703-05
« Last post by Mason1 on August 03, 2021, 06:28:00 PM »
Thanks for the answer, I realized there are two VCCIOB, one is connected to J1B-B32 and the other one is connected to J8. Turns out the J8 one was shorted to 3.3 V through a jumper and the 2.5 V that I was giving to J1B-B32 did not change that voltage (probably because my power supply was cutting the circuit). I removed the jumper of J8 and the circuit started producing LVDS outputs (attached). I have a 100 Ohm resistor and the output voltage is within the range.


I am going to design the PCB and will provide the Bank #34 VCCIO through pin J1B-32, I hope this pin is capable of passing enough current to this bank in order to do MHz LVDS. Thanks again for your help!
2
Trenz Electronic FPGA Modules / Re: TEI0001-03-08-C8 (MAX1000) board
« Last post by Thomas D on July 30, 2021, 12:48:20 PM »
Hi,
I already answered to a very similar question here: https://forum.trenz-electronic.de/index.php?topic=1288.msg6133#msg6133
At the moment I can't help more on this topic, I'm sorry.

br
Thomas
3
Trenz Electronic FPGA Modules / Re: LVDS with TE0711 mounted on TE0703-05
« Last post by JH on July 30, 2021, 07:23:01 AM »
Hi,
Quote
with "input" as a ~100 Hz sample clock.
is this a typo? You mean 100MHz?

Quote
the VCCIOB is connected to bank 35 (Screenshot is attached). This pin is connected to J1B-B32 on the carrier board.
Carrier pinout is a general one for different modules. This notes was left from carrier designer, as carrier was design for annother 4x5 module.
So pay attention with the names on carriers.
We offer a pinout excel:
https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/Pinout
4x5_series_pinout_tracelength.xlsx


back to your problem. So when DIFF_HSTL_I works, I think you use correct pins.
Bank 34 supply is from JM2-1/3 this is carrier JB2-2,4  --> VCCIOB. J8 Jumper for VCCIOB can only set to 1.8V or 3.3V (see carrier schematic page 2), so you use external supply for 2,5V, that's ok.
Can you check one time that your voltage is correct?
https://www.xilinx.com/support/answers/43989.html


You did measure only differential or? When you measure single ended, did you see the CM level? This should be around 1.25V, see ds181 page 11

br
John
4
Trenz Electronic FPGA Modules / TEI0001-03-08-C8 (MAX1000) board
« Last post by emerrryjones on July 30, 2021, 05:23:33 AM »
Hi everyone,

I'm using a TEI0001-03-08-C8 (MAX1000) board with a NIOSII softcore and running applications on it.

Is it possible to do Remote System Upgrade over UART and store it on the external W74M64 flash and run it from the external W9864G6JT SDRAM with a bootloader in the internal flash?

What are the steps to do this in QSYS?

This could be a nice DEMO addition for the MAX1000 boards!

Thanks in advance!!!
5
Trenz Electronic FPGA Modules / Re: LVDS with TE0711 mounted on TE0703-05
« Last post by Mason1 on July 29, 2021, 03:20:37 PM »
Sounds like the link takes you to another document, sorry for the inconvenience, here is the correct link:

https://shop.trenz-electronic.de/trenzdownloads/Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0703/REV06/Documents/SCH-TE0703-06-D.PDF
6
Trenz Electronic FPGA Modules / LVDS with TE0711 mounted on TE0703-05
« Last post by Mason1 on July 28, 2021, 11:56:51 PM »
Hi Forum,

I am trying to get an LVDS output on I/O Bank 34 (from a TE0711 mounted on a TE0703-05). First, I make sure there is no CMOS pin connected to this bank, then I go ahead and define the constraint like this:

Code: [Select]
set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVDS_25} [get_ports outn]; # J1-A28 IO_L7N_T1_34
set_property -dict {PACKAGE_PIN U1 IOSTANDARD LVDS_25} [get_ports outp]; # J1-A29 IO_L7P_T1_34

and I define the output port like this:

Code: [Select]
lvds_clk_0 : OBUFDS   -- LVDS clock
generic map (
    IOSTANDARD => "DEFAULT")    -- Specify the output I/O standard
port map (
    O => outp,     -- Diff_p output (connect directly to top-level port)
    OB => outn,    -- Diff_n output (connect directly to top-level port)
    I => input                 -- Buffer input
);

with "input" as a ~100 Hz sample clock. I also include the following libraries in my code:
Code: [Select]
library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.NUMERIC_STD.ALL;

library UNISIM;
    use UNISIM.VComponents.all;


I should connect the I/O Bank 34 VCCIO to 2.5 V, as mentioned on page 2 of TRM-TE0711-0 [https://shop.trenz-electronic.de/trenzdownloads/Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0703/REV06/Documents/SCH-TE0703-06-D.PDF] the VCCIOB is connected to bank 35 (Screenshot is attached). This pin is connected to J1B-B32 on the carrier board.

I connect a 2.5 V to this pin and program the device, outp and outn are shorted through a 100 Ohm resistor (this resistor models the termination resistor). Unfortunately, I do not see an output, as you can see in the oscilloscope screenshot (attached) both outputs are zero. I tried using a differential (non-LVDS output like DIFF_HSTL_I and it works well meaning that I see a differential output between outp and outn. Am I missing something or am I making a mistake here? Thanks.




7
Hi,
Quote
Also tried to get more info from https://wiki.trenz-electronic.de/display/PD/Board+bring-up+overview+for+TEI0022#BoardbringupoverviewforTEI0022-SDcardsetup
However, it requires log-in info, which I cannot obtain.

The link to the "SD card setup" website was incorrect. You can find this website here:

br
Thomas
8
Thanks John,
 
The DDR size was set correctly to 0x08000000. I have checked it.
I did some further debug and found through printenv. Below is a dump of my printenv.
I notice that the bootm_size is still set to 40000000 (shown below)

Code: [Select]
--------------------------------------------------------------------------------
Xilinx First Stage Boot Loader (TE modified)
Release 2020.2  Jul 22 2021-08:54:45

Device IDCODE: 23727093
Device Name: 7z020 (7)
Device Revision: 2
--------------------------------------------------------------------------------
TE0720 TE_FsblHookBeforeHandoff_Custom

SoM: TE0720-03-1C  R SC REV:05
MAC: D8 80 39 4A 40 DE

--------------------------------------------------------------------------------


U-Boot 2020.01 (Jul 22 2021 - 08:55:39 +0000)

CPU:   Zynq 7z020
Silicon: v3.1
DRAM:  ECC disabled 1 GiB
Flash: 0 Bytes
NAND:  0 MiB
MMC:   mmc@e0100000: 0
In:    serial@e0000000
Out:   serial@e0000000
Err:   serial@e0000000
Net:
ZYNQ GEM: e000b000, mdio bus e000b000, phyaddr 0, interface rgmii-id

Warning: ethernet@e000b000 using MAC address from DT
eth0: ethernet@e000b000
Hit any key to stop autoboot:  0
Zynq> printenv
arch=arm
baudrate=115200
board=zynq
board_name=zynq
boot_a_script=load ${devtype} ${devnum}:${distro_bootpart} ${scriptaddr} ${prefix}${script}; source ${scriptaddr}
boot_efi_binary=if fdt addr ${fdt_addr_r}; then bootefi bootmgr ${fdt_addr_r};else bootefi bootmgr ${fdtcontroladdr};fi;load ${devtype} ${devnum}:${distro_bootpart} ${kernel_addr_r} efi/boot/bootarm.efi; if fdt addr ${fdt_addr_r}; then bootefi ${kernel_addr_r} ${fdt_addr_r};else bootefi ${kernel_addr_r} ${fdtcontroladdr};fi
boot_extlinux=sysboot ${devtype} ${devnum}:${distro_bootpart} any ${scriptaddr} ${prefix}${boot_syslinux_conf}
boot_net_usb_start=usb start
boot_prefixes=/ /boot/
boot_script_dhcp=boot.scr.uimg
boot_scripts=boot.scr.uimg boot.scr
boot_syslinux_conf=extlinux/extlinux.conf
boot_targets=mmc0 jtag mmc0 mmc1 qspi nand nor usb0 usb1 pxe dhcp
bootcmd=run distro_bootcmd
bootcmd_dhcp=run boot_net_usb_start; if dhcp ${scriptaddr} ${boot_script_dhcp}; then source ${scriptaddr}; fi;setenv efi_fdtfile ${fdtfile}; if test -z "${fdtfile}" -a -n "${soc}"; then setenv efi_fdtfile ${soc}-${board}${boardver}.dtb; fi; setenv efi_old_vci ${bootp_vci};setenv efi_old_arch ${bootp_arch};setenv bootp_vci PXEClient:Arch:00010:UNDI:003000;setenv bootp_arch 0xa;if dhcp ${kernel_addr_r}; then tftpboot ${fdt_addr_r} dtb/${efi_fdtfile};if fdt addr ${fdt_addr_r}; then bootefi ${kernel_addr_r} ${fdt_addr_r}; else bootefi ${kernel_addr_r} ${fdtcontroladdr};fi;fi;setenv bootp_vci ${efi_old_vci};setenv bootp_arch ${efi_old_arch};setenv efi_fdtfile;setenv efi_old_arch;setenv efi_old_vci;
bootcmd_jtag=echo JTAG: Trying to boot script at ${scriptaddr} && source ${scriptaddr}; echo JTAG: SCRIPT FAILED: continuing...;
bootcmd_mmc0=devnum=0; run mmc_boot
bootcmd_mmc1=devnum=1; run mmc_boot
bootcmd_nand=nand info && nand read ${scriptaddr} ${script_offset_f} ${script_size_f} && echo NAND: Trying to boot script at ${scriptaddr} && source ${scriptaddr}; echo NAND: SCRIPT FAILED: continuing...;
bootcmd_nor=cp.b ${script_offset_nor} ${scriptaddr} ${script_size_f} && echo NOR: Trying to boot script at ${scriptaddr} && source ${scriptaddr}; echo NOR: SCRIPT FAILED: continuing...;
bootcmd_pxe=run boot_net_usb_start; dhcp; if pxe get; then pxe boot; fi
bootcmd_qspi=sf probe 0 0 0 && sf read ${scriptaddr} ${script_offset_f} ${script_size_f} && echo QSPI: Trying to boot script at ${scriptaddr} && source ${scriptaddr}; echo QSPI: SCRIPT FAILED: continuing...;
bootcmd_usb0=devnum=0; run usb_boot
bootcmd_usb1=devnum=1; run usb_boot
bootdelay=2
bootm_low=0
bootm_size=40000000
cpu=armv7
dfu_mmc=run dfu_mmc_info && dfu 0 mmc 0
dfu_mmc_info=setenv dfu_alt_info ${kernel_image} fat 0 1\\;${devicetree_image} fat 0 1\\;${ramdisk_image} fat 0 1
dfu_ram=run dfu_ram_info && dfu 0 ram 0
dfu_ram_info=setenv dfu_alt_info ${kernel_image} ram 0x3000000 0x500000\\;${devicetree_image} ram 0x2A00000 0x20000\\;${ramdisk_image} ram 0x2000000 0x600000
distro_bootcmd=for target in ${boot_targets}; do run bootcmd_${target}; done
efi_dtb_prefixes=/ /dtb/ /dtb/current/
ethaddr=00:0a:35:00:1e:53
fdt_addr_r=0x1f00000
fdt_high=0x20000000
fdtcontroladdr=3eb09888
initrd_high=0x20000000
kernel_addr_r=0x2000000
load_efi_dtb=load ${devtype} ${devnum}:${distro_bootpart} ${fdt_addr_r} ${prefix}${efi_fdtfile}
mmc_boot=if mmc dev ${devnum}; then devtype=mmc; run scan_dev_for_boot_part; fi
modeboot=sdboot
pxefile_addr_r=0x2000000
ramdisk_addr_r=0x3100000
scan_dev_for_boot=echo Scanning ${devtype} ${devnum}:${distro_bootpart}...; for prefix in ${boot_prefixes}; do run scan_dev_for_extlinux; run scan_dev_for_scripts; done;run scan_dev_for_efi;
scan_dev_for_boot_part=part list ${devtype} ${devnum} -bootable devplist; env exists devplist || setenv devplist 1; for distro_bootpart in ${devplist}; do if fstype ${devtype} ${devnum}:${distro_bootpart} bootfstype; then run scan_dev_for_boot; fi; done; setenv devplist
scan_dev_for_efi=setenv efi_fdtfile ${fdtfile}; if test -z "${fdtfile}" -a -n "${soc}"; then setenv efi_fdtfile ${soc}-${board}${boardver}.dtb; fi; for prefix in ${efi_dtb_prefixes}; do if test -e ${devtype} ${devnum}:${distro_bootpart} ${prefix}${efi_fdtfile}; then run load_efi_dtb; fi;done;if test -e ${devtype} ${devnum}:${distro_bootpart} efi/boot/bootarm.efi; then echo Found EFI removable media binary efi/boot/bootarm.efi; run boot_efi_binary; echo EFI LOAD FAILED: continuing...; fi; setenv efi_fdtfile
scan_dev_for_extlinux=if test -e ${devtype} ${devnum}:${distro_bootpart} ${prefix}${boot_syslinux_conf}; then echo Found ${prefix}${boot_syslinux_conf}; run boot_extlinux; echo SCRIPT FAILED: continuing...; fi
scan_dev_for_scripts=for script in ${boot_scripts}; do if test -e ${devtype} ${devnum}:${distro_bootpart} ${prefix}${script}; then echo Found U-Boot script ${prefix}${script}; run boot_a_script; echo SCRIPT FAILED: continuing...; fi; done
script_offset_f=fc0000
script_offset_nor=0xE2FC0000
script_size_f=0x40000
scriptaddr=0x3000000
soc=zynq
stderr=serial@e0000000
stdin=serial@e0000000
stdout=serial@e0000000
thor_mmc=run dfu_mmc_info && thordown 0 mmc 0
thor_ram=run dfu_ram_info && thordown 0 ram 0
usb_boot=usb start; if usb dev ${devnum}; then devtype=usb; run scan_dev_for_boot_part; fi
vendor=xilinx

Environment size: 5200/131068 bytes


Then I changed the value and try to start again

Code: [Select]
Zynq> setenv bootm_size 0x08000000
Zynq> fatload mmc 0 0x01000000 image.ub
11548776 bytes read in 648 ms (17 MiB/s)
Zynq> bootm 0x01000000

This is what I observe. Definitely seems to have gone further than before and hangs after the CPU0 is up.

Code: [Select]
## Loading kernel from FIT Image at 01000000 ...
   Using 'conf@system-top.dtb' configuration
   Verifying Hash Integrity ... OK
   Trying 'kernel@1' kernel subimage
     Description:  Linux kernel
     Type:         Kernel Image
     Compression:  uncompressed
     Data Start:   0x010000f8
     Data Size:    4327800 Bytes = 4.1 MiB
     Architecture: ARM
     OS:           Linux
     Load Address: 0x00200000
     Entry Point:  0x00200000
     Hash algo:    sha256
     Hash value:   a64f3da06ea7e181a36bb210c52acff5fa12af0a63f2108a423a3118fe8351c5
   Verifying Hash Integrity ... sha256+ OK
## Loading ramdisk from FIT Image at 01000000 ...
   Using 'conf@system-top.dtb' configuration
   Verifying Hash Integrity ... OK
   Trying 'ramdisk@1' ramdisk subimage
     Description:  petalinux-image-minimal
     Type:         RAMDisk Image
     Compression:  uncompressed
     Data Start:   0x01426280
     Data Size:    7196788 Bytes = 6.9 MiB
     Architecture: ARM
     OS:           Linux
     Load Address: unavailable
     Entry Point:  unavailable
     Hash algo:    sha256
     Hash value:   43815dc9cfd3e9bdcc067301caeae38741f48bc83238538ed69a3d3cb3c0d5db
   Verifying Hash Integrity ... sha256+ OK
## Loading fdt from FIT Image at 01000000 ...
   Using 'conf@system-top.dtb' configuration
   Verifying Hash Integrity ... OK
   Trying 'fdt@system-top.dtb' fdt subimage
     Description:  Flattened Device Tree blob
     Type:         Flat Device Tree
     Compression:  uncompressed
     Data Start:   0x01420b7c
     Data Size:    22071 Bytes = 21.6 KiB
     Architecture: ARM
     Hash algo:    sha256
     Hash value:   3dc5567fde128fb2b75f9d6b5c6371389b0cdeca1e348a093c9f4b19da270ea2
   Verifying Hash Integrity ... sha256+ OK
   Booting using the fdt blob at 0x1420b7c
   Loading Kernel Image
   Loading Ramdisk to 07922000, end 07fff074 ... OK
   Loading Device Tree to 07919000, end 07921636 ... OK
Starting kernel ...

Booting Linux on physical CPU 0x0
Linux version 5.4.0-xilinx-v2020.2 (oe-user@oe-host) (gcc version 9.2.0 (GCC)) #1 SMP PREEMPT Thu Jul 22 08:55:55 UTC 2021
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
OF: fdt: Machine model: xlnx,zynq-7000
earlycon: cdns0 at MMIO 0xe0000000 (options '115200n8')
printk: bootconsole [cdns0] enabled
Memory policy: Data cache writealloc
cma: Reserved 16 MiB at 0x3f000000
percpu: Embedded 15 pages/cpu s31948 r8192 d21300 u61440
Built 1 zonelists, mobility grouping on.  Total pages: 260416
Kernel command line: console=ttyPS0,115200 earlycon root=/dev/ram0 rw
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes, linear)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
mem auto-init: stack:off, heap alloc:off, heap free:off
Memory: 1003852K/1048576K available (6144K kernel code, 217K rwdata, 1844K rodata, 1024K init, 131K bss, 28340K reserved, 16384K cma-reserved, 245760K highmem)
rcu: Preemptible hierarchical RCU implementation.
rcu:    RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
        Tasks RCU enabled.
rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
efuse mapped to (ptrval)
slcr mapped to (ptrval)
L2C: platform modifies aux control register: 0x72360000 -> 0x72760000
L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000
L2C-310 erratum 769419 enabled
L2C-310 enabling early BRESP for Cortex-A9
L2C-310 full line of zeros enabled for Cortex-A9
L2C-310 ID prefetch enabled, offset 1 lines
L2C-310 dynamic clock gating enabled, standby mode enabled
L2C-310 cache controller enabled, 8 ways, 512 kB
L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001
random: get_random_bytes called from start_kernel+0x260/0x440 with crng_init=0
zynq_clock_init: clkc starts at (ptrval)
Zynq clock init
sched_clock: 64 bits at 333MHz, resolution 3ns, wraps every 4398046511103ns
clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x4ce07af025, max_idle_ns: 440795209040 ns
Switching to timer-based delay loop, resolution 3ns
Console: colour dummy device 80x30
Calibrating delay loop (skipped), value calculated using timer frequency.. 666.66 BogoMIPS (lpj=3333333)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 2048 (order: 1, 8192 bytes, linear)
Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes, linear)
CPU: Testing write buffer coherency: ok
CPU0: Spectre v2: using BPIALL workaround
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000


Do I need to make some change in the device tree for the software system to detect the change in memory size as suggested below?
https://forums.xilinx.com/t5/Embedded-Linux/How-to-change-the-memory-size-with-linux/td-p/874873

Thanks,
Neels
9
Hi,
was the DDR size correctly set in the petalinux config menue?
--> Subsystem Auto HW settings ..> Memory Settings

br
John
10
Hi John,

The suggestion you provided solved the issue in the example design provided by trenz.
When I tried to make the same change to my custom design (adapted from trenz),
the imageub_addr changes from 0x10000000 to 0x8000000
but the boot process is still halting (indefinitely) while loading the Ramdisk as shown below.

Code: [Select]
U-Boot 2020.01 (Jul 21 2021 - 12:22:46 +0000)

CPU:   Zynq 7z020
Silicon: v3.1
DRAM:  ECC disabled 1 GiB
Flash: 0 Bytes
NAND:  0 MiB
MMC:   mmc@e0100000: 0
In:    serial@e0000000
Out:   serial@e0000000
Err:   serial@e0000000
Net:
ZYNQ GEM: e000b000, mdio bus e000b000, phyaddr 0, interface rgmii-id

Warning: ethernet@e000b000 using MAC address from DT
eth0: ethernet@e000b000
Hit any key to stop autoboot:  0
switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
Found U-Boot script /boot.scr
2010 bytes read in 22 ms (88.9 KiB/s)
## Executing script at 03000000
11549096 bytes read in 647 ms (17 MiB/s)
## Loading kernel from FIT Image at 08000000 ...
   Using 'conf@system-top.dtb' configuration
   Verifying Hash Integrity ... OK
   Trying 'kernel@1' kernel subimage
     Description:  Linux kernel
     Type:         Kernel Image
     Compression:  uncompressed
     Data Start:   0x080000f8
     Data Size:    4327792 Bytes = 4.1 MiB
     Architecture: ARM
     OS:           Linux
     Load Address: 0x00200000
     Entry Point:  0x00200000
     Hash algo:    sha256
     Hash value:   6bd266db40ac3f6752d7b17b53692980a6e3701c6b1fe259c81a20bb27a52d40
   Verifying Hash Integrity ... sha256+ OK
## Loading ramdisk from FIT Image at 08000000 ...
   Using 'conf@system-top.dtb' configuration
   Verifying Hash Integrity ... OK
   Trying 'ramdisk@1' ramdisk subimage
     Description:  petalinux-image-minimal
     Type:         RAMDisk Image
     Compression:  uncompressed
     Data Start:   0x08426278
     Data Size:    7197116 Bytes = 6.9 MiB
     Architecture: ARM
     OS:           Linux
     Load Address: unavailable
     Entry Point:  unavailable
     Hash algo:    sha256
     Hash value:   7e879a71c37268ceb7d70344d271484713bf7f956ebe48ef21a2421086093227
   Verifying Hash Integrity ... sha256+ OK
## Loading fdt from FIT Image at 08000000 ...
   Using 'conf@system-top.dtb' configuration
   Verifying Hash Integrity ... OK
   Trying 'fdt@system-top.dtb' fdt subimage
     Description:  Flattened Device Tree blob
     Type:         Flat Device Tree
     Compression:  uncompressed
     Data Start:   0x08420b74
     Data Size:    22071 Bytes = 21.6 KiB
     Architecture: ARM
     Hash algo:    sha256
     Hash value:   3dc5567fde128fb2b75f9d6b5c6371389b0cdeca1e348a093c9f4b19da270ea2
   Verifying Hash Integrity ... sha256+ OK
   Booting using the fdt blob at 0x8420b74
   Loading Kernel Image
   Loading Ramdisk to 1f922000, end 1ffff1bc ...


What is really puzzling is the specific address to where the Ramdisk loads, I think the address shown below is not valid (as my device has only 256 MB).
I have been trying to find the location from where the address is coming from, but yet to find them.
Do you have some idea from where this address is coming from ?

Code: [Select]
    Loading Kernel Image
    Loading Ramdisk to 1f922000, end 1ffff1bc ...

The reason why I am interested in changing the address to which the Ramdisk loads is that,
I have seen that when the example design works the Ramdisk was loading to (0e42b000 - 0eb07fd0) as shown below.
Code: [Select]
   Loading Kernel Image
   Loading Ramdisk to 0e42b000, end 0eb07fd0 ... OK
   Loading Device Tree to 0e423000, end 0e42ae14 ... OK

   Starting kernel ...

Thanks,
Neels
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