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#1
EDDP-EDPS Support / Re: [TE0950] QSFP help
Last post by M Kirberg - November 14, 2025, 09:17:20 AMHi,
we have no experience with this core or application, but a non locking core warning does not sound good to me. What frequency did you set?
Regarding the additional signals, I also would say optional/default level is good enough for you. However to be sure measure the QSFP_RESET voltage on R73 as a double check.
br
we have no experience with this core or application, but a non locking core warning does not sound good to me. What frequency did you set?
Regarding the additional signals, I also would say optional/default level is good enough for you. However to be sure measure the QSFP_RESET voltage on R73 as a double check.
br
#2
EDDP-EDPS Support / Re: [TE0950] QSFP help
Last post by hw-lab - November 13, 2025, 01:05:39 PMGood morning Markus.
From our understanding, the i2c configuration is completely optional, so we are ignoring it for now. Please correct me if I'm wrong.
However we would like to know if the remaining QSFP+ management signals (nRESET, nMODSEL, LPMODE) have to be driven to a specific value.
- Do we need to set LPMODE to some precise value? We already tried setting it to '0' with a quick modification to the Artix design, without success.
- We know that nRESET has a pull-up resistor inside the cable/QSFP+ module, so driving it is optional.
- We know that nMODSEL is auxiliary for the i2c bus (works like a chip select), but we are not using the i2c bus.
Here is a not-so-brief summary of what we are doing:
We are connecting the TE0950-03 board to an ethernet/SFP+ switch using this passive cable: https://it.rs-online.com/web/p/connettori-io-ad-innesto/1881446
We are using the Xilinx XXV ethernet core with DMA to PS memory, together with the Xilinx ethernet driver included in Petalinux. The interface shows up in linux as eth0, we are able to assign an address and bring up the interface, but the ethernet/SFP+ switch does not detect the link.
The SFP+ slots of the switch were tested and are all working correctly.
Linux commands:
sudo ip link set dev eth0 up
sudo ip addr add 10.1.1.1/24 dev eth0
The following error appears in the boot log, and every time we bring up the interface:
[time] xilinx_axienet 80000000.ethernet eth0: XXV MAC block lock not complete! Cross-check the MAC ref clock configuration
We found other boot logs of example projects on the internet, where this error appears, but the 25G connection works without issues.
Also, the Xilinx FAE we contacted thinks this is more like a warning, and should not prevent the XXV MAC from working.
After trying to ping another address on the subnet, ifconfig shows:
...
UP BROADCAST RUNNING MTU:1500 Metric:1
RX packets:0 errors:0 dropped:0 overruns:0 frame:0
TX packets:92 errors:0 dropped:0 overruns:0 frame:0
...
Thank you for your time, have a nice day
From our understanding, the i2c configuration is completely optional, so we are ignoring it for now. Please correct me if I'm wrong.
However we would like to know if the remaining QSFP+ management signals (nRESET, nMODSEL, LPMODE) have to be driven to a specific value.
- Do we need to set LPMODE to some precise value? We already tried setting it to '0' with a quick modification to the Artix design, without success.
- We know that nRESET has a pull-up resistor inside the cable/QSFP+ module, so driving it is optional.
- We know that nMODSEL is auxiliary for the i2c bus (works like a chip select), but we are not using the i2c bus.
Here is a not-so-brief summary of what we are doing:
We are connecting the TE0950-03 board to an ethernet/SFP+ switch using this passive cable: https://it.rs-online.com/web/p/connettori-io-ad-innesto/1881446
We are using the Xilinx XXV ethernet core with DMA to PS memory, together with the Xilinx ethernet driver included in Petalinux. The interface shows up in linux as eth0, we are able to assign an address and bring up the interface, but the ethernet/SFP+ switch does not detect the link.
The SFP+ slots of the switch were tested and are all working correctly.
Linux commands:
sudo ip link set dev eth0 up
sudo ip addr add 10.1.1.1/24 dev eth0
The following error appears in the boot log, and every time we bring up the interface:
[time] xilinx_axienet 80000000.ethernet eth0: XXV MAC block lock not complete! Cross-check the MAC ref clock configuration
We found other boot logs of example projects on the internet, where this error appears, but the 25G connection works without issues.
Also, the Xilinx FAE we contacted thinks this is more like a warning, and should not prevent the XXV MAC from working.
After trying to ping another address on the subnet, ifconfig shows:
...
UP BROADCAST RUNNING MTU:1500 Metric:1
RX packets:0 errors:0 dropped:0 overruns:0 frame:0
TX packets:92 errors:0 dropped:0 overruns:0 frame:0
...
Thank you for your time, have a nice day
#3
EDDP-EDPS Support / Re: [TE0950] QSFP help
Last post by M Kirberg - November 13, 2025, 11:32:01 AMHi,
the reference design already includes an AxiSmart Connect design for Artix.
Regarding QSFP and the Artix: is it that you want to use the Control Signals and/or I2C?
I2C is already wired, the control signals could be used by wiring them to an GPIO Controller similar what is already done for Cruvi Signals.
br
Markus Kirberg
the reference design already includes an AxiSmart Connect design for Artix.
Regarding QSFP and the Artix: is it that you want to use the Control Signals and/or I2C?
I2C is already wired, the control signals could be used by wiring them to an GPIO Controller similar what is already done for Cruvi Signals.
br
Markus Kirberg
#4
Trenz Electronic FPGA Modules / Re: Andromeda PHY not detected
Last post by M Kirberg - November 12, 2025, 12:41:31 PMHi,
the PHY uses the LEDs as strapping pins. So during reset the Pullups on the AM0010 have to be strong enough, they are 4K7.
So on the baseboard there should not be something pulling down (or at least with more resistance than 4K7 Ohm)
This is also an Error in the AMB0010 Carrier which will be fixed by increasing R38 and R39 to 10kOhm with a PCN
the PHY uses the LEDs as strapping pins. So during reset the Pullups on the AM0010 have to be strong enough, they are 4K7.
So on the baseboard there should not be something pulling down (or at least with more resistance than 4K7 Ohm)
This is also an Error in the AMB0010 Carrier which will be fixed by increasing R38 and R39 to 10kOhm with a PCN
#5
EDDP-EDPS Support / [TE0950] QSFP help
Last post by hw-lab - November 11, 2025, 10:48:40 PMGood evening all!
Recently at my office we bought two TE0950 dev boards.
At the moment we have successfully built the reference design with Petelinux and Vivado 2024.2.
Now, starting from the ref. des., we want to explore the QSFP interface by using the Ethernet Subsystem IP configured at 10 Gbps and use it by means of Petalinux. The idea is to start with the reference design of the Eth Subsystem and integrate it with the TE0950 reference design by means of an AXI Smart Connect.
Is there some advice that we have to follow in terms of clock configuration and/or the Artix FPGA design?
Thanks in advance,
Antonio
Recently at my office we bought two TE0950 dev boards.
At the moment we have successfully built the reference design with Petelinux and Vivado 2024.2.
Now, starting from the ref. des., we want to explore the QSFP interface by using the Ethernet Subsystem IP configured at 10 Gbps and use it by means of Petalinux. The idea is to start with the reference design of the Eth Subsystem and integrate it with the TE0950 reference design by means of an AXI Smart Connect.
Is there some advice that we have to follow in terms of clock configuration and/or the Artix FPGA design?
Thanks in advance,
Antonio
#6
Trenz Electronic FPGA Modules / Re: Andromeda PHY not detected
Last post by CTSchorsch - November 07, 2025, 01:31:56 PMHi @akarcher,
can you go a little bit more in details how you fixed this issue ? I have a similiar problem with my phy addr
Thanks
Georg
can you go a little bit more in details how you fixed this issue ? I have a similiar problem with my phy addr
Thanks
Georg
#7
Trenz Electronic FPGA Modules / Re: PS->PL EMIO 1 GbE to SFP f...
Last post by paul - November 06, 2025, 08:15:17 PMFor those who might come across this thread later: the issue was the polarity of the MGT diffpair used for 1000BASE-X (MGT_TX3_P/N and MGT_RX3_P/N) is swapped between the TE0715-05 SOM and the TEBA0841 carrier card.
Enabling the transceiver control and status ports (see attached) and driving both gt0_txpolarity_in and gt0_rxpolarity_in high solved the problem for me.
Clock configuration was fine and handled properly by Trenz's code in FSBL.
Thank you John and Mohsen for your help!
Paul
Enabling the transceiver control and status ports (see attached) and driving both gt0_txpolarity_in and gt0_rxpolarity_in high solved the problem for me.
Clock configuration was fine and handled properly by Trenz's code in FSBL.
Thank you John and Mohsen for your help!
Paul
#8
Trenz Electronic FPGA Modules / Re: PS->PL EMIO 1 GbE to SFP f...
Last post by mch - November 05, 2025, 12:40:05 PMHi Paul,
Are you using our reference design?
https://wiki.trenz-electronic.de/display/PD/TE0715+Test+Board
https://www.trenz-electronic.de/Downloads/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0715/Reference_Design/2023.2/test_board
Which Vivado revision are you using?
We program the PLL chip (U10 SI5338) in our reference design using FSBL during booting via I2C interface. You can find the configuration core of the PLL in the FSBL source code in the "sw_lib" folder in our reference design folder.
The problem that the ethernet phy chip in your design cannot be found may be due to resetting. You should reset the ethernet phy chip in FSBL. The reset pin of the ethernet phy chip is connected to MIO50 in the hardware. You can use the AMD API commands in the FSBL code to reset the ethernet phy chip. If you are using our reference design, we did not reset the ethernet phy chip in FSBL code.
If you look in the "misc/si5338" folder, you will find the ClockBuilder project file for the PLL chip. We have selected IN3 with a frequency of 25MHz as the default input clock to generate a clock with a frequency of 125MHz.
Best regards,
Mohsen Chamanbaz
Are you using our reference design?
https://wiki.trenz-electronic.de/display/PD/TE0715+Test+Board
https://www.trenz-electronic.de/Downloads/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0715/Reference_Design/2023.2/test_board
Which Vivado revision are you using?
We program the PLL chip (U10 SI5338) in our reference design using FSBL during booting via I2C interface. You can find the configuration core of the PLL in the FSBL source code in the "sw_lib" folder in our reference design folder.
The problem that the ethernet phy chip in your design cannot be found may be due to resetting. You should reset the ethernet phy chip in FSBL. The reset pin of the ethernet phy chip is connected to MIO50 in the hardware. You can use the AMD API commands in the FSBL code to reset the ethernet phy chip. If you are using our reference design, we did not reset the ethernet phy chip in FSBL code.
If you look in the "misc/si5338" folder, you will find the ClockBuilder project file for the PLL chip. We have selected IN3 with a frequency of 25MHz as the default input clock to generate a clock with a frequency of 125MHz.
Best regards,
Mohsen Chamanbaz
#9
UltraScale / Re: TE0821 with TE0706 Carrier...
Last post by M Kirberg - November 05, 2025, 12:38:22 PMPlease look at the boot mode setting on the TE0821 CPLD. Setting S1:3 is not enough you need to be in JTAG mode thats what the error says, and you are most likely in QSPI mode.
PGOOD is used as additional bootmode pin in standard firmware, you need to "set" this signal also to the right value.
PGOOD is used as additional bootmode pin in standard firmware, you need to "set" this signal also to the right value.
#10
Trenz Electronic FPGA Modules / Re: Does TE0720 Ethernet work ...
Last post by viktornikolov - November 02, 2025, 01:21:52 PMQuote from: viktornikolov on October 28, 2025, 07:23:01 PMI don't know what's wrong with my MirkoTik switch.
There is nothing wrong with my switch. 😀
The lwIP works OK with the MikroTik switch. There is no issue with the ADC check forced by enabling the lwip220_lwip_dhcp_does_acd_check BSP option.
I was getting the "ERROR: DHCP request timed out" simply because the process of the switch offering an IP address to the Zynq board and the board doing the ACD check took more than 12 seconds. When I modified the code to extend the time limit to 16 seconds, everything worked fine.
It seems MirkoTik switches are not very fast at assigning an IP address via DHCP. The default RouterOS DHCP Server configuration includes conflict detection (the switch performs an ARP probe before assigning an IP address to a client).