Trenz Electronic GmbH Support Forum

Trenz Electronic Products => Trenz Electronic FPGA Modules => Topic started by: GuinnessTrinker on June 21, 2012, 12:47:19 PM

Title: Recommended starting point for EDK-based designs
Post by: GuinnessTrinker on June 21, 2012, 12:47:19 PM
Recommended starting point for EDK-based designs
http://www.trenz-electronic.de/download/d0/Trenz_Electronic/d1/TE0600-GigaBee_series/d2/TE0600/d3/reference_designs.html

"When upgrading to ISE XMP v13.3 or higher, we reccommend NOT to upgrade the AXI_ETHERNET core to v3.00.a, as we could not get it work!"

Are there any news regarding this issue?
Did someone get it work on 13.4?

Title: Re: Recommended starting point for EDK-based designs
Post by: Ales Gorkic on June 21, 2012, 10:03:05 PM
HI GuinnessTrinker,

We tried the newer version of the of the AXI_ETHERNET in ISE 13.4 but it did not work out of the box.
But one of our customers replied that it was working when he did the upgrade.
You are more than welcome to try it out. We would like to get some feedback also about implementation in the latest 14.1 tools.

But watch out for one very nasty bug in the 13.3 EDK tools: when using multiple clock_generator cores in Spartan 6 it fails to route (MCB PLL reset routing problems). That is why the recommended toolchain is 13.3 or 14.1.

Best regards

Ales