Hi all,
I got a project where the customer wants to implement (and already bought the module) a GigaBee XC6SLXmodule.
My question is: how do I implement an external (differential) LVDS external clock (bit-clock coming from 100/125 MHz ADC).
The clock for the ADC is created on my motherboard.
My thoughts are using pins
IO_L34P_GCLK19_0 (B2B_B0_L34_N) J2 46
IO_L34N_GCLK18_0 (B2B_B0_L34_P) J2 48
as differential clock inputs.
Can you please confirm whether this is possible, as I read that only the use of the internal 125MHz clock was...?
Kind regards,
Robert.
Dear Robert,
There is no problem receiving the LVDS clock from the ADC.
You need IBUFGDS primitive for clock buffering (from manual spartan6_hdl.pdf) if you use VHDL:
-- IBUFGDS: Differential Global Clock Input Buffer
--Spartan-6
-- Xilinx HDL Libraries Guide, version 13.2
IBUFGDS_inst : IBUFGDS
generic map (
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "LVDS_33")
port map (
O => O, -- Clock buffer output
I => I, -- Diff_p clock buffer input (connect directly to top-level port)
IB => IB -- Diff_n clock buffer input (connect directly to top-level port)
);
-- End of IBUFGDS_inst instantiation
Please set the proper termination value (TRUE if you do not have external termination resistor) and IOSTANDARD (LVDS_25 or LVDS_33)
in ucf you need to specify pins:
NET IB LOC=A10; #B2B_B0_L34_N
NET I LOC=B10; #B2B_B0_L34_P
The buffer output "O" you either route directly to capture circuit or via DCM for precise phase alignment (adjustable during operation...).
Best regards,
Ales