I have an Artix-7 TE0713_100_2C module on a TE0703-05 carrier board.
I took the module's reference design which contains the AXI Quad SPI IP Core:
https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0713/Reference_Design/2016.4/test_board (https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0713/Reference_Design/2016.4/test_board)
I added the JTAG to AXI Master IP Core to have easy access to it from within Vivado. I can write the bitstream to the boot prom from Vivado's "Hardware Manager" and boot from it, so the chip seems to be functioning properly.
I can access all the registers of the IP core, but I can't read back anything from the SPI chip using the AXI Quad SPI IP core. All I get back is 0xFF.
An example what I am trying is also in the Xilinx application note xapp1280, which contains a script called jtag_to_qspi.tcl, see attachment.
This script should read the ID from the boot prom using the 0x9F command. But this also fails.
The boot prom chip on this boad is a Spansion/Cypress S25FL256S
I read that this chip in not in Quad mode by default.
Is this chip still in quad SPI mode after configuration? Or should I put it in quad SPI mode ?
Does anyone know how I can but it in quad mode using the AXI Quad SPI core ?
Does anyone have other hints on using the AXI Quad SPI core to access the boot prom on the TE0713 ?
Any help would be greatly appreciated.
Kind regards,
Ronald
Hi,
you want to get access to the QSPI flash on the module --> S25FL256SAGBHI20?
Did you use board automation of QSPI IP configuration and IO loc constrains or did you initialise by yourself? How is the IP configured?
br
John
The AXI Quad SPI was already part of the reference design. (See link in previous post)
Configured, connected and all. I made no changes to it.
I did manage to gain access to the QSPI flash. The TCL file from xapp1280 was on the right track but contained a few flaws that did not make it work. Most notably the burst read commands should have included the "-burst FIXED" argument. Since the default burst type is "incremental" and the reads should all be read from the same RX FIFO register. See https://www.xilinx.com/support/documentation/ip_documentation/jtag_axi/v1_2/pg174-jtag-axi.pdf (https://www.xilinx.com/support/documentation/ip_documentation/jtag_axi/v1_2/pg174-jtag-axi.pdf)
Hi,
good to hear that it works and thank you for the hints.
br
John