Hello,
I have created a simple design based on the test_board example in Vivado 2018.2 for a TE0720-03-1CF module.
Base board is the TE0701.
I launched the SDK after exporting the design.
From there I created an application, as via the instructions, FSBL and HelloWorld.
For creation of the image I included the PL bit-file.
When I try to program the flash
cmd /C program_flash -f \
C:\Users\Precision\Documents\project_1\project_1.sdk\TrenzHelloSw\bootimage\TrenzHello.bin \
-offset 0 -flash_type qspi_single -fsbl \
C:\Users\Precision\Documents\project_1\project_1.sdk\HelloWorld\Debug\HelloWorld.elf \
-verify -cable type xilinx_tcf url TCP:127.0.0.1:3121
I get :
****** Xilinx Program Flash
****** Program Flash v2018.2 (64-bit)
**** SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
Connected to hw_server @ TCP:127.0.0.1:3121
Available targets and devices:
Target 0 : jsn-JTAG-ONB4-251633000746A
Device 0: jsn-JTAG-ONB4-251633000746A-4ba00477-0
Retrieving Flash info...
Initialization done, programming the memory
===== mrd->addr=0xF800025C, data=0x00000001 =====
BOOT_MODE REG = 0x00000001
WARNING: [Xicom 50-100] The current boot mode is QSPI.
If flash programming fails, configure device for JTAG boot mode and try again.
===== mrd->addr=0xF8007080, data=0x30800100 =====
===== mrd->addr=0xF8000B18, data=0x80008000 =====
Downloading FSBL...
===== mrd->addr=0xF8000110, data=0x00177EA0 =====
READ: ARM_PLL_CFG (0xF8000110) = 0x00177EA0
===== mrd->addr=0xF8000100, data=0x0001A008 =====
READ: ARM_PLL_CTRL (0xF8000100) = 0x0001A008
===== mrd->addr=0xF8000120, data=0x1F000400 =====
READ: ARM_CLK_CTRL (0xF8000120) = 0x1F000400
===== mrd->addr=0xF8000118, data=0x00177EA0 =====
READ: IO_PLL_CFG (0xF8000118) = 0x00177EA0
===== mrd->addr=0xF8000108, data=0x0001A008 =====
READ: IO_PLL_CTRL (0xF8000108) = 0x0001A008
Problem in Initializing Hardware
Flash programming initialization failed.
ERROR: Flash Operation Failed
I have tried the default Xilinx zynq_fsbl and Trenz zynq_fsbl_flash.
Results do not differ.
What do I do wrong ?
best regards
Simon
Hi,
your first log file:
Quote
cmd /C program_flash -f \
C:\Users\Precision\Documents\project_1\project_1.sdk\TrenzHelloSw\bootimage\TrenzHello.bin \
-offset 0 -flash_type qspi_single -fsbl \
C:\Users\Precision\Documents\project_1\project_1.sdk\HelloWorld\Debug\HelloWorld.elf \
-verify -cable type xilinx_tcf url TCP:127.0.0.1:3121
in case you used special FSBL provided by the reference design, did you use the correct one from the prebuilt folder?
Or did you generate the boot.bin included the special FSBL fro QSPI? --> In this case it's wrong, this special FSBL it's for the GUI and is used only for PS initialisation during micro uboot access to QSPI flash. Use normal FSBL on boot.bin.
br
John
Hello,
I have the same problem with the TE0782 board. I got the answer of Xilinx that without setting the boot mode to JTAC it is not possible to program the QSPI on a Zynq anymore:
https://forums.xilinx.com/t5/Embedded-Boot-and-Configuration/Vivado-2018-2-gt-unable-to-reprogram-QSPI-via-JTAG-in-QSPI32/m-p/890256/highlight/false#M1332
It there a possible way to change the bootmode with e.g. a "debug" CPLD firmware on the TE0782?
Thank you!
Regards, Stephan
Hi,
for vivado 2017.3 and newer you need a special FSBL which must be selected only on the GUI of Vivado or SDK, see:
- https://wiki.trenz-electronic.de/pages/viewpage.action?pageId=14746264#Vivado/SDK/SDSoC-XilinxSoftware-ProductUpdateReleaseNotesandKnownIssues
- https://www.xilinx.com/support/answers/70148.html (https://www.xilinx.com/support/answers/70148.html)
Problem on this changes from Xilinx is, that default FSBL try to find a Boot.bin on QSPI. And if Flash is empty, it will stop on an error state, before QSPI will be programmed by Xilinx micro Uboot.
So use Boot.bin with "normal" FSBL and create a second one for the Vivado/SDK GUI only.
On the second one, you must only overwrite boot mode register readback on main.c:
/*
* Read bootmode register
*/
BootModeRegister = Xil_In32(BOOT_MODE_REG);
BootModeRegister &= BOOT_MODES_MASK;
/* TE Mod : */
BootModeRegister = JTAG_MODE;
/* TE Mod : finished*/
Optional you can also disable DDR initialisation, because it's not needed for QSPI configuration.
At the moment we have for TE0782 only 2017.1 reference design but I will update to 2018.2 as soon as possible, so you can also this one when I've finished design update.
brJohn
Thank you for that explination. Now it works!
Regards, Stephan
We have it working as well !
Thanks,
Simon