Hierarchy Input Constant Input Unused Input Floating Input Output Constant Output Unused Output Floating Output Bidir Constant Bidir Unused Bidir Input only Bidir Output only Bidir
u0|rst_controller|alt_rst_req_sync_uq1 2 1 0 1 1 1 1 1 0 0 0 0 0
u0|rst_controller|alt_rst_sync_uq1 2 0 0 0 1 0 0 0 0 0 0 0 0
u0|rst_controller 33 31 0 31 1 31 31 31 0 0 0 0 0
u0|avalon_st_adapter|channel_adapter_0 22 0 2 0 20 0 0 0 0 0 0 0 0
u0|avalon_st_adapter 22 0 0 0 20 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_001|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_001 38 0 0 0 37 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter 38 0 0 0 37 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|rsp_mux|arb|adder 8 4 0 4 4 4 4 4 0 0 0 0 0
u0|mm_interconnect_0|rsp_mux|arb 6 0 4 0 2 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|rsp_mux 185 0 0 0 93 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|rsp_demux_001 94 1 2 1 92 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|rsp_demux 94 1 2 1 92 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_001 94 0 2 0 92 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux 94 0 2 0 92 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_demux 95 4 2 4 183 4 4 4 0 0 0 0 0
u0|mm_interconnect_0|router_002|the_default_decode 0 2 0 2 2 2 2 2 0 0 0 0 0
u0|mm_interconnect_0|router_002 92 0 2 0 92 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|router_001|the_default_decode 0 2 0 2 2 2 2 2 0 0 0 0 0
u0|mm_interconnect_0|router_001 92 0 2 0 92 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|router|the_default_decode 0 3 0 3 3 3 3 3 0 0 0 0 0
u0|mm_interconnect_0|router 92 0 3 0 92 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|modular_adc_0_sequencer_csr_agent_rsp_fifo 132 39 0 39 91 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|modular_adc_0_sequencer_csr_agent|uncompressor 30 1 0 1 28 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|modular_adc_0_sequencer_csr_agent 259 39 39 39 276 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|altpll_0_pll_slave_agent_rsp_fifo 132 39 0 39 91 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|altpll_0_pll_slave_agent|uncompressor 30 1 0 1 28 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|altpll_0_pll_slave_agent 259 39 39 39 276 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|avalon_adc_0_avalon_master_agent 153 31 60 31 124 31 31 31 0 0 0 0 0
u0|mm_interconnect_0|modular_adc_0_sequencer_csr_translator 99 6 15 6 69 6 6 6 0 0 0 0 0
u0|mm_interconnect_0|altpll_0_pll_slave_translator 99 6 14 6 70 6 6 6 0 0 0 0 0
u0|mm_interconnect_0|avalon_adc_0_avalon_master_translator 100 17 0 17 92 17 17 17 0 0 0 0 0
u0|mm_interconnect_0 116 0 0 0 104 0 0 0 0 0 0 0 0
u0|modular_adc_0|sequencer_internal|u_seq_ctrl 8 0 0 0 9 0 0 0 0 0 0 0 0
u0|modular_adc_0|sequencer_internal|u_seq_csr 38 0 28 0 37 0 0 0 0 0 0 0 0
u0|modular_adc_0|sequencer_internal 39 1 0 1 40 1 1 1 0 0 0 0 0
u0|modular_adc_0|control_internal|adc_inst|adcblock_instance 9 0 0 0 14 0 0 0 0 0 0 0 0
u0|modular_adc_0|control_internal|adc_inst|decoder 5 0 0 0 5 0 0 0 0 0 0 0 0
u0|modular_adc_0|control_internal|adc_inst 9 0 0 0 14 0 0 0 0 0 0 0 0
u0|modular_adc_0|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|wr_ptr 4 0 0 0 6 0 0 0 0 0 0 0 0
u0|modular_adc_0|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|rd_ptr_count 4 0 0 0 6 0 0 0 0 0 0 0 0
u0|modular_adc_0|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|FIFOram 28 0 0 0 12 0 0 0 0 0 0 0 0
u0|modular_adc_0|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw 5 0 0 0 6 0 0 0 0 0 0 0 0
u0|modular_adc_0|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|fifo_state 5 0 0 0 2 0 0 0 0 0 0 0 0
u0|modular_adc_0|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo 16 0 0 0 14 0 0 0 0 0 0 0 0
u0|modular_adc_0|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated 16 0 0 0 14 0 0 0 0 0 0 0 0
u0|modular_adc_0|control_internal|u_control_fsm|ts_avrg_fifo 16 0 0 0 12 0 0 0 0 0 0 0 0
u0|modular_adc_0|control_internal|u_control_fsm 26 0 0 0 30 0 0 0 0 0 0 0 0
u0|modular_adc_0|control_internal 13 1 0 1 21 1 1 1 0 0 0 0 0
u0|modular_adc_0 39 0 0 0 52 0 0 0 0 0 0 0 0
u0|avalon_adc_0 55 0 35 0 67 0 0 0 0 0 0 0 0
u0|altpll_0|sd1 3 1 0 1 6 1 1 1 0 0 0 0 0
u0|altpll_0|stdsync2|dffpipe3 3 0 0 0 1 0 0 0 0 0 0 0 0
u0|altpll_0|stdsync2 3 0 0 0 1 0 0 0 0 0 0 0 0
u0|altpll_0 48 40 30 40 34 40 40 40 0 0 0 0 0
u0 2 1 0 1 17 1 1 1 0 0 0 0 0