---

altpll_0

altpll v20.1

Parameters HIDDEN_CUSTOM_ELABORATION altpll_avalon_elaboration HIDDEN_CUSTOM_POST_EDIT altpll_avalon_post_edit INTENDED_DEVICE_FAMILY MAX 10 WIDTH_CLOCK 5 WIDTH_PHASECOUNTERSELECT PRIMARY_CLOCK INCLK0_INPUT_FREQUENCY 83333 INCLK1_INPUT_FREQUENCY OPERATION_MODE NORMAL PLL_TYPE AUTO QUALIFY_CONF_DONE COMPENSATE_CLOCK CLK0 SCAN_CHAIN GATE_LOCK_SIGNAL GATE_LOCK_COUNTER LOCK_HIGH LOCK_LOW VALID_LOCK_MULTIPLIER INVALID_LOCK_MULTIPLIER SWITCH_OVER_ON_LOSSCLK SWITCH_OVER_ON_GATED_LOCK ENABLE_SWITCH_OVER_COUNTER SKIP_VCO SWITCH_OVER_COUNTER SWITCH_OVER_TYPE FEEDBACK_SOURCE BANDWIDTH BANDWIDTH_TYPE AUTO SPREAD_FREQUENCY DOWN_SPREAD SELF_RESET_ON_GATED_LOSS_LOCK SELF_RESET_ON_LOSS_LOCK CLK0_MULTIPLY_BY 5 CLK1_MULTIPLY_BY CLK2_MULTIPLY_BY CLK3_MULTIPLY_BY CLK4_MULTIPLY_BY CLK5_MULTIPLY_BY CLK6_MULTIPLY_BY CLK7_MULTIPLY_BY CLK8_MULTIPLY_BY CLK9_MULTIPLY_BY EXTCLK0_MULTIPLY_BY EXTCLK1_MULTIPLY_BY EXTCLK2_MULTIPLY_BY EXTCLK3_MULTIPLY_BY CLK0_DIVIDE_BY 6 CLK1_DIVIDE_BY CLK2_DIVIDE_BY CLK3_DIVIDE_BY CLK4_DIVIDE_BY CLK5_DIVIDE_BY CLK6_DIVIDE_BY CLK7_DIVIDE_BY CLK8_DIVIDE_BY CLK9_DIVIDE_BY EXTCLK0_DIVIDE_BY EXTCLK1_DIVIDE_BY EXTCLK2_DIVIDE_BY EXTCLK3_DIVIDE_BY CLK0_PHASE_SHIFT 0 CLK1_PHASE_SHIFT CLK2_PHASE_SHIFT CLK3_PHASE_SHIFT CLK4_PHASE_SHIFT CLK5_PHASE_SHIFT CLK6_PHASE_SHIFT CLK7_PHASE_SHIFT CLK8_PHASE_SHIFT CLK9_PHASE_SHIFT EXTCLK0_PHASE_SHIFT EXTCLK1_PHASE_SHIFT EXTCLK2_PHASE_SHIFT EXTCLK3_PHASE_SHIFT CLK0_DUTY_CYCLE 50 CLK1_DUTY_CYCLE CLK2_DUTY_CYCLE CLK3_DUTY_CYCLE CLK4_DUTY_CYCLE CLK5_DUTY_CYCLE CLK6_DUTY_CYCLE CLK7_DUTY_CYCLE CLK8_DUTY_CYCLE CLK9_DUTY_CYCLE EXTCLK0_DUTY_CYCLE EXTCLK1_DUTY_CYCLE EXTCLK2_DUTY_CYCLE EXTCLK3_DUTY_CYCLE PORT_clkena0 PORT_UNUSED PORT_clkena1 PORT_UNUSED PORT_clkena2 PORT_UNUSED PORT_clkena3 PORT_UNUSED PORT_clkena4 PORT_UNUSED PORT_clkena5 PORT_UNUSED PORT_extclkena0 PORT_extclkena1 PORT_extclkena2 PORT_extclkena3 PORT_extclk0 PORT_UNUSED PORT_extclk1 PORT_UNUSED PORT_extclk2 PORT_UNUSED PORT_extclk3 PORT_UNUSED PORT_CLKBAD0 PORT_UNUSED PORT_CLKBAD1 PORT_UNUSED PORT_clk0 PORT_USED PORT_clk1 PORT_UNUSED PORT_clk2 PORT_UNUSED PORT_clk3 PORT_UNUSED PORT_clk4 PORT_UNUSED PORT_clk5 PORT_UNUSED PORT_clk6 PORT_clk7 PORT_clk8 PORT_clk9 PORT_SCANDATA PORT_UNUSED PORT_SCANDATAOUT PORT_UNUSED PORT_SCANDONE PORT_UNUSED PORT_SCLKOUT1 PORT_SCLKOUT0 PORT_ACTIVECLOCK PORT_UNUSED PORT_CLKLOSS PORT_UNUSED PORT_INCLK1 PORT_UNUSED PORT_INCLK0 PORT_USED PORT_FBIN PORT_UNUSED PORT_PLLENA PORT_UNUSED PORT_CLKSWITCH PORT_UNUSED PORT_ARESET PORT_UNUSED PORT_PFDENA PORT_UNUSED PORT_SCANCLK PORT_UNUSED PORT_SCANACLR PORT_UNUSED PORT_SCANREAD PORT_UNUSED PORT_SCANWRITE PORT_UNUSED PORT_ENABLE0 PORT_ENABLE1 PORT_LOCKED PORT_USED PORT_CONFIGUPDATE PORT_UNUSED PORT_FBOUT PORT_PHASEDONE PORT_UNUSED PORT_PHASESTEP PORT_UNUSED PORT_PHASEUPDOWN PORT_UNUSED PORT_SCANCLKENA PORT_UNUSED PORT_PHASECOUNTERSELECT PORT_UNUSED PORT_VCOOVERRANGE PORT_VCOUNDERRANGE DPA_MULTIPLY_BY DPA_DIVIDE_BY DPA_DIVIDER VCO_MULTIPLY_BY VCO_DIVIDE_BY SCLKOUT0_PHASE_SHIFT SCLKOUT1_PHASE_SHIFT VCO_FREQUENCY_CONTROL VCO_PHASE_SHIFT_STEP USING_FBMIMICBIDIR_PORT SCAN_CHAIN_MIF_FILE AVALON_USE_SEPARATE_SYSCLK NO HIDDEN_CONSTANTS CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_UNUSED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 5 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 83333 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 6 CT#PORT_LOCKED PORT_USED HIDDEN_PRIVATES PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 12.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ0 10.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE 8 PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE0 10.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK4 0 PT#STICKY_CLK3 0 PT#STICKY_CLK2 0 PT#STICKY_CLK1 0 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK0 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#CLKLOSS_CHECK 0 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE0 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1609796220452977.mif PT#ACTIVECLK_CHECK 0 HIDDEN_USED_PORTS UP#locked used UP#c0 used UP#areset used UP#inclk0 used HIDDEN_IS_NUMERIC IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#PLL_ENHPLL_CHECK 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 HIDDEN_MF_PORTS MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1 HIDDEN_IF_PORTS IF#phasecounterselect {input 3} IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#phaseupdown {input 0} IF#scandone {output 0} IF#readdata {output 32} IF#write {input 0} IF#scanclk {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#c2 {output 0} IF#address {input 2} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0} IF#scanclkena {input 0} IF#scandataout {output 0} IF#configupdate {input 0} IF#phasestep {input 0} IF#scandata {input 0} HIDDEN_IS_FIRST_EDIT 0 AUTO_DEVICE_FAMILY MAX10FPGA AUTO_INCLK_INTERFACE_CLOCK_RATE 50000000 deviceFamily MAX 10 generateLegacySim false

  

Software Assignments (none)

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avalon_ADC_0

avalon_ADC v1.0

Parameters deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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clk_0

clock_source v20.1

Parameters clockFrequency 50000000 clockFrequencyKnown true inputClockFrequency 0 resetSynchronousEdges NONE deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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modular_adc_0

altera_modular_adc v20.1

Parameters CORE_VAR 2 ENABLE_DEBUG 0 MONITOR_COUNT_WIDTH 12 CLOCK_FREQ 50000000 FAMILY MAX10FPGA DEVICE_PART 10M08SAU169C8G device_partname_fivechar_prefix 10M08 device_adc_type 22 max_adc_count_on_die 1 adc_count_on_device 1 device_power_supply_type 1 ip_is_for_which_adc 1 is_this_first_or_second_adc 1 analog_input_pin_mask 0 hard_pwd 0 sample_rate 0 clkdiv 2 derived_clkdiv 2 tsclkdiv 1 tsclksel 1 refsel 1 external_vref 2.5 int_vref_vr 3.0 int_vref_nonvr 2.5 reference_voltage 3.0 reference_voltage_sim 65536 prescalar 0 enable_usr_sim 0 use_tsd false en_tsd_max false tsd_max 125 en_tsd_min false tsd_min 0 use_ch0 true en_thmax_ch0 false thmax_ch0 0.0 en_thmin_ch0 false thmin_ch0 0.0 simfilename_ch0 use_ch1 true en_thmax_ch1 false thmax_ch1 0.0 en_thmin_ch1 false thmin_ch1 0.0 simfilename_ch1 use_ch2 false en_thmax_ch2 false thmax_ch2 0.0 en_thmin_ch2 false thmin_ch2 0.0 simfilename_ch2 use_ch3 false en_thmax_ch3 false thmax_ch3 0.0 en_thmin_ch3 false thmin_ch3 0.0 simfilename_ch3 use_ch4 false en_thmax_ch4 false thmax_ch4 0.0 en_thmin_ch4 false thmin_ch4 0.0 simfilename_ch4 use_ch5 false en_thmax_ch5 false thmax_ch5 0.0 en_thmin_ch5 false thmin_ch5 0.0 simfilename_ch5 use_ch6 false en_thmax_ch6 false thmax_ch6 0.0 en_thmin_ch6 false thmin_ch6 0.0 simfilename_ch6 use_ch7 false en_thmax_ch7 false thmax_ch7 0.0 en_thmin_ch7 false thmin_ch7 0.0 simfilename_ch7 use_ch8 false prescaler_ch8 false en_thmax_ch8 false thmax_ch8 0.0 en_thmin_ch8 false thmin_ch8 0.0 simfilename_ch8 use_ch9 false en_thmax_ch9 false thmax_ch9 0.0 en_thmin_ch9 false thmin_ch9 0.0 simfilename_ch9 use_ch10 false en_thmax_ch10 false thmax_ch10 0.0 en_thmin_ch10 false thmin_ch10 0.0 simfilename_ch10 use_ch11 false en_thmax_ch11 false thmax_ch11 0.0 en_thmin_ch11 false thmin_ch11 0.0 simfilename_ch11 use_ch12 false en_thmax_ch12 false thmax_ch12 0.0 en_thmin_ch12 false thmin_ch12 0.0 simfilename_ch12 use_ch13 false en_thmax_ch13 false thmax_ch13 0.0 en_thmin_ch13 false thmin_ch13 0.0 simfilename_ch13 use_ch14 false en_thmax_ch14 false thmax_ch14 0.0 en_thmin_ch14 false thmin_ch14 0.0 simfilename_ch14 use_ch15 false en_thmax_ch15 false thmax_ch15 0.0 en_thmin_ch15 false thmin_ch15 0.0 simfilename_ch15 use_ch16 false prescaler_ch16 false en_thmax_ch16 false thmax_ch16 0.0 en_thmin_ch16 false thmin_ch16 0.0 simfilename_ch16 seq_order_length 1 seq_order_slot_1 1 seq_order_slot_2 6 seq_order_slot_3 2 seq_order_slot_4 4 seq_order_slot_5 8 seq_order_slot_6 5 seq_order_slot_7 7 seq_order_slot_8 1 seq_order_slot_9 8 seq_order_slot_10 30 seq_order_slot_11 30 seq_order_slot_12 30 seq_order_slot_13 30 seq_order_slot_14 30 seq_order_slot_15 30 seq_order_slot_16 30 seq_order_slot_17 30 seq_order_slot_18 30 seq_order_slot_19 30 seq_order_slot_20 30 seq_order_slot_21 30 seq_order_slot_22 30 seq_order_slot_23 30 seq_order_slot_24 30 seq_order_slot_25 30 seq_order_slot_26 30 seq_order_slot_27 30 seq_order_slot_28 30 seq_order_slot_29 30 seq_order_slot_30 30 seq_order_slot_31 30 seq_order_slot_32 30 seq_order_slot_33 30 seq_order_slot_34 30 seq_order_slot_35 30 seq_order_slot_36 30 seq_order_slot_37 30 seq_order_slot_38 30 seq_order_slot_39 30 seq_order_slot_40 30 seq_order_slot_41 30 seq_order_slot_42 30 seq_order_slot_43 30 seq_order_slot_44 30 seq_order_slot_45 30 seq_order_slot_46 30 seq_order_slot_47 30 seq_order_slot_48 30 seq_order_slot_49 30 seq_order_slot_50 30 seq_order_slot_51 30 seq_order_slot_52 30 seq_order_slot_53 30 seq_order_slot_54 30 seq_order_slot_55 30 seq_order_slot_56 30 seq_order_slot_57 30 seq_order_slot_58 30 seq_order_slot_59 30 seq_order_slot_60 30 seq_order_slot_61 30 seq_order_slot_62 30 seq_order_slot_63 30 seq_order_slot_64 30 AUTO_DEVICE_SPEEDGRADE 8 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments CORE_VARIANT 2 CSD_LENGTH 1 CSD_SLOT_0 CH1 CSD_SLOT_1 CH0 CSD_SLOT_10 CH0 CSD_SLOT_11 CH0 CSD_SLOT_12 CH0 CSD_SLOT_13 CH0 CSD_SLOT_14 CH0 CSD_SLOT_15 CH0 CSD_SLOT_16 CH0 CSD_SLOT_17 CH0 CSD_SLOT_18 CH0 CSD_SLOT_19 CH0 CSD_SLOT_2 CH0 CSD_SLOT_20 CH0 CSD_SLOT_21 CH0 CSD_SLOT_22 CH0 CSD_SLOT_23 CH0 CSD_SLOT_24 CH0 CSD_SLOT_25 CH0 CSD_SLOT_26 CH0 CSD_SLOT_27 CH0 CSD_SLOT_28 CH0 CSD_SLOT_29 CH0 CSD_SLOT_3 CH0 CSD_SLOT_30 CH0 CSD_SLOT_31 CH0 CSD_SLOT_32 CH0 CSD_SLOT_33 CH0 CSD_SLOT_34 CH0 CSD_SLOT_35 CH0 CSD_SLOT_36 CH0 CSD_SLOT_37 CH0 CSD_SLOT_38 CH0 CSD_SLOT_39 CH0 CSD_SLOT_4 CH0 CSD_SLOT_40 CH0 CSD_SLOT_41 CH0 CSD_SLOT_42 CH0 CSD_SLOT_43 CH0 CSD_SLOT_44 CH0 CSD_SLOT_45 CH0 CSD_SLOT_46 CH0 CSD_SLOT_47 CH0 CSD_SLOT_48 CH0 CSD_SLOT_49 CH0 CSD_SLOT_5 CH0 CSD_SLOT_50 CH0 CSD_SLOT_51 CH0 CSD_SLOT_52 CH0 CSD_SLOT_53 CH0 CSD_SLOT_54 CH0 CSD_SLOT_55 CH0 CSD_SLOT_56 CH0 CSD_SLOT_57 CH0 CSD_SLOT_58 CH0 CSD_SLOT_59 CH0 CSD_SLOT_6 CH0 CSD_SLOT_60 CH0 CSD_SLOT_61 CH0 CSD_SLOT_62 CH0 CSD_SLOT_63 CH0 CSD_SLOT_7 CH0 CSD_SLOT_8 CH0 CSD_SLOT_9 CH0 DUAL_ADC_MODE false PRESCALER_CH16 0 PRESCALER_CH8 0 REFSEL Internal VREF USE_CH0 1 USE_CH1 1 USE_CH10 0 USE_CH11 0 USE_CH12 0 USE_CH13 0 USE_CH14 0 USE_CH15 0 USE_CH16 0 USE_CH2 0 USE_CH3 0 USE_CH4 0 USE_CH5 0 USE_CH6 0 USE_CH7 0 USE_CH8 0 USE_CH9 0 USE_TSD 0 VREF 3.0