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1

Trenz Electronic FPGA Modules / Re: TE0720 custom carrier - Petalinux (2020.2) issues

« Last post by M Kirberg on Today at 09:23:17 AM »

What do you mean "make a clean of the recipe"? How do I do that?

Code: [Select]

petalinux-build -c kernel -x cleanall

I do see this new message when the kernel boots:
Code: [Select]
[Firmware Warn]: /amba/ethernet@e000b000/mdio/phy@0: Whitelisted compatible string. Please remove

Is this normal?

Yes, you can remove the compatible string in your phy node, as it is no longer needed in newer Kernel versions. This is only a warning and no error.

Also, about the device tree. Where are all the pieces located? The only parts I can find, that do not say they are automatically generated, are in .../os/project-spec/meta-user/recipes-bsp/device-tree/files. Those files are system-user.dtsi and pl-custom.dtsi.

system-user.dtsi is what you specifically add. Xilinx uses automatic generation based on your .xsa file, and therefore already adds stuff in you PL which it knows.
One way to see what is generated is to decompile your devicetree, and inspect it.
On your device you may use

Code: [Select]

dtc -I fs /sys/firmware/devicetree/base to decompile it.

2

Trenz Electronic FPGA Modules / Re: TE0720 custom carrier - Petalinux (2020.2) issues

« Last post by bigguiness on January 26, 2023, 06:07:51 PM »

Thanks for the reply and link.

I have made the configuration changes to petalinux and u-boot as described. I also updated the device tree, that should fix the RTC issue.

What do you mean "make a clean of the recipe"? How do I do that?

When I did a petalinux-build after making the config changes I now get:

Code: [Select]

WARNING: .../os/components/yocto/layers/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2020.2.bb:do_compile is tainted from a forced run
WARNING: .../os/components/yocto/layers/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2020.2.bb:do_compile is tainted from a forced run

I just booted the new build and the MAC address is now correct. Also the RTC is working now.

I do see this new message when the kernel boots:

Code: [Select]

[Firmware Warn]: /amba/ethernet@e000b000/mdio/phy@0: Whitelisted compatible string. Please remove
Is this normal?

Also, about the device tree. Where are all the pieces located? The only parts I can find, that do not say they are automatically generated, are in .../os/project-spec/meta-user/recipes-bsp/device-tree/files. Those files are system-user.dtsi and pl-custom.dtsi.

I have an AXI_GPIO block in my design. Two of the outputs from that block drive some LEDs on my board. I want to bind them to gpio-leds in the kernel but can't figure out how to do it.

Thanks

3

Trenz Electronic FPGA Modules / Re: TE0720 custom carrier - Petalinux (2020.2) issues

« Last post by M Kirberg on January 26, 2023, 11:29:26 AM »

Is the WARNING telling me that the build did not use the updated kernel config? Or am I missing something else to get the ISL12020 working?

yes, you can make a clean of the recipe to avoid this


Regarding the MAC: the passing of FSBL to UBOOT only works if you use the U-Boot settings from

https://wiki.trenz-electronic.de/display/PD/TE0720+Test+Board#TE0720TestBoard-U-Boot

4

Trenz Electronic FPGA Modules / Re: TE0720 custom carrier - Petalinux (2020.2) issues

« Last post by bigguiness on January 26, 2023, 01:11:40 AM »

One other thing...

I noticed that I was not seeing the "Xilinx First Stage Boot Loader (TE modified)" stuff when my board powers on. I was just seeing:

Code: [Select]

U-Boot 2020.01 (Jan 25 2023 - 18:40:56 +0000)

CPU:   Zynq 7z020
Silicon: v3.1
DRAM:  ECC disabled 1 GiB
Flash: 0 Bytes
NAND:  0 MiB
MMC:   mmc@e0100000: 0, mmc@e0101000: 1
Loading Environment from SPI Flash... SF: Detected s25fl256s1 with page size 256 Bytes, erase size 64 KiB, total 32 MiB
*** Warning - bad CRC, using default environment

In:    serial@e0000000
Out:   serial@e0000000
Err:   serial@e0000000
Net:   
ZYNQ GEM: e000b000, mdio bus e000b000, phyaddr -1, interface rgmii-id

Warning: ethernet@e000b000 using MAC address from DT
eth0: ethernet@e000b000
Hit any key to stop autoboot:  0

In the BSP directory I found that the ./project-spec/meta-user/recipes-bsp/u-boot stuff was a bit different and there is a ./project-spec/meta-user/recipes-bsp/fsbl that was not in my petalinux setup. I copied those two directories to my setup and rebuilt petalinux. Now I see the FSBL stuff when the board powers on:

Code: [Select]

--------------------------------------------------------------------------------
Xilinx First Stage Boot Loader (TE modified)
Release 2020.2  Jan 25 2023-23:59:51

Device IDCODE: 23727093
Device Name: 7z020 (7)
Device Revision: 2
--------------------------------------------------------------------------------
TE0720 TE_FsblHookBeforeHandoff_Custom

SoM: TE0720-03-1C  F SC REV:05
MAC: D8 80 39 DE 31 20

--------------------------------------------------------------------------------


U-Boot 2020.01 (Jan 25 2023 - 23:59:29 +0000)

CPU:   Zynq 7z020
Silicon: v3.1
DRAM:  ECC disabled 1 GiB
Flash: 0 Bytes
NAND:  0 MiB
MMC:   mmc@e0100000: 0, mmc@e0101000: 1
In:    serial@e0000000
Out:   serial@e0000000
Err:   serial@e0000000
Net:   
ZYNQ GEM: e000b000, mdio bus e000b000, phyaddr -1, interface rgmii-id

Warning: ethernet@e000b000 using MAC address from DT
eth0: ethernet@e000b000
Hit any key to stop autoboot:  0

But the Ethernet MAC is not getting set correctly. During the kernel boot I see:

Code: [Select]

Marvell 88E1510 e000b000.ethernet-ffffffff:00: attached PHY driver [Marvell 88E1510] (mii_bus:phy_addr=e000b000.ethernet-ffffffff:00, irq=POLL)
macb e000b000.ethernet eth0: Cadence GEM rev 0x00020118 at 0xe000b000 irq 29 (00:0a:35:00:1e:53)

And after booting 'ifconfig' shows this:

Code: [Select]

root@s6:~# ifconfig
eth0      Link encap:Ethernet  HWaddr 00:0A:35:00:1E:53 
          inet addr:10.168.0.97  Bcast:10.168.0.255  Mask:255.255.255.0
          inet6 addr: fe80::20a:35ff:fe00:1e53/64 Scope:Link
          UP BROADCAST RUNNING MULTICAST  MTU:1500  Metric:1
          RX packets:31 errors:0 dropped:0 overruns:0 frame:0
          TX packets:32 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:2621 (2.5 KiB)  TX bytes:5328 (5.2 KiB)
          Interrupt:29 Base address:0xb000

lo        Link encap:Local Loopback 
          inet addr:127.0.0.1  Mask:255.0.0.0
          inet6 addr: ::1/128 Scope:Host
          UP LOOPBACK RUNNING  MTU:65536  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:0 (0.0 B)  TX bytes:0 (0.0 B)

What am I missing to get the HWaddr set properly?

Thanks

5

Trenz Electronic FPGA Modules / TE0720 custom carrier - Petalinux (2020.2) issues

« Last post by bigguiness on January 25, 2023, 06:45:27 PM »

Hello,

I have tested my hardware design using Vitis as far as I can. Now I'm trying to setup a Petalinux system starting from scratch (not using one of the Trenz BSP packages).

I was able to get the hardware to boot, after having an issue with the serial ports and then fixing it, by doing:

Code: [Select]

$ source /tools/Xilinx/Petalinux/2020.2/settings.sh
$ petalinux-create --type project --template zynq --name os
$ cd os
$ petalinux-config --get-hw-description ../

# The default config sets up the FSBL and DTG Serial stdin/stdout as (ps7_uart_1). I had to change it to (ps7_uart_0) for the TE0720 board.
$ petalinux-config

$ petalinux-build
$ petalinux-package --boot --fsbl images/linux/zynq_fsbl.elf --fpga images/linux/system.bit --u-boot --force
(Simple enough, other than having to do it twice because of the serial port issue...)

I then copied to files to a prepared SD-card and was able to boot the system. But after booting I noticed that rtc0 (the ISL12020 chip on the TE0720) was not detected. The necessary driver is not enabled by default in the kernel so I modified the kernel config to build in the driver and then rebuilt petalinux.

Code: [Select]

$ petalinux-config -c kernel
$ petalinux-buildDuring the petalinux build I get this warning:

Code: [Select]

WARNING: .../os/components/yocto/layers/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2020.2.bb:do_compile is tainted from a forced run
When I packaged the output and tried booting the system, rtc0 was still not found.

Is the WARNING telling me that the build did not use the updated kernel config? Or am I missing something else to get the ISL12020 working?

Thanks

6

Trenz Electronic FPGA Modules / TE0712 JTAG Question

« Last post by matix on January 25, 2023, 01:22:38 PM »

Hello
I have TE0712 board with TE0701-6 carrier. I wrote code in Vitis, and flashed it through USB into flash memory including bitstream. Problem is that project does not work as it supposed to. My question is  are there possibilities to program and debug TE0712 using miniUSB JTAG? If programming with JTAG is not possible is there at least one option just to debug microblaze with USB?

Also have you got any ideas why uartlite with interrupts in baremetal application does not receive all data? It goes in interrupt and then receive some data, ale most of them are lost. I have tried a lot, reset fifo, disable interrupt during ISR, read by bytes, read whole register, check status in while loop to have prove that uartlite report having some data in regs. All in all i think that almost every possible combinations were tested with no success.

7

Trenz Electronic FPGA Modules / Re: TE0715-4 and usb 1-1 device descriptor read/64, error -71

« Last post by Waldi3141 on January 24, 2023, 06:17:04 PM »

nice to hear that
Thanks for presenting your solution!

8

Trenz Electronic FPGA Modules / Re: TE0715-4 and usb 1-1 device descriptor read/64, error -71

« Last post by RobbieT on January 24, 2023, 04:56:50 PM »

Final update. replaced L87 and cleaned traces to USB with flux on the TE0701 board.
Most probably due to usage issue on this carrier board from my side.
All is operational now and USB stick are recognized. (also under original 2018.2 build).
Many thanks for your support.

9

Trenz Electronic FPGA Modules / Re: regarding modifying kernel in petalinux 2021.2 version

« Last post by M Kirberg on January 24, 2023, 09:27:00 AM »

Hi,

you do not have to do anything. Petalinux (Yocto) creates a kernel-config fragment in the directory meta-user\recipes-kernel\linux\linux-xlnx for you.
This will be merged to reach a final .config.

However, in your case this does not seem to be the case.
Specifically what setting are you trying to achieve (CONFIG_XXX=n) ?

If you need more debugging possibilities you can use the underlying bitbake with tasks like:
https://docs.yoctoproject.org/singleindex.html#do-kernel-configcheck

see https://docs.xilinx.com/r/en-US/ug1144-petalinux-tools-reference-guide/Accessing-BitBake/Devtool-in-a-Project for how to fire up bitbake for your petalinux project.

Best,
Markus

10

Trenz Electronic FPGA Modules / Re: TE0725 3.3v power supply pins.

« Last post by Trenz0691 on January 22, 2023, 04:58:22 AM »

Thanks @Waldi3141