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91
Open source hardware / Re: How can i program with K150 isp
« Last post by JH on August 31, 2022, 11:48:17 AM »
Hi,
this forum is only for Trenz Electronic products. Therefore, we can't help you there either.
You should ask the manufacturer directly or write to some more general forum...for example:
https://forum.hobbycomponents.com/viewtopic.php?f=49&t=1830
br
John
92
Hi,
can it be that you has different problems?
on one of your first logs, linux has memory allocation problem...but now Uboot can't find phy over MDIO, so either phy address is wrong or your connection the the PHY over PL or maybe your phy is in reset?
br
John
93
Trenz Electronic FPGA Modules / Re: Linux USB problems with TE0720-03-2IF on TE0701
« Last post by JH on August 31, 2022, 09:42:44 AM »
Hi,
I haven't 720 on place at the moment. Can you boot one time with our design and check which drivers are load (and/or share log also here).
Code: [Select]
usbcore: registered new interface driver uas
usbcore: registered new interface driver usb-storage
usbcore: registered new interface driver usbserial
usbcore: registered new interface driver usbserial_generic
usbserial: USB Serial support registered for generic
usbcore: registered new interface driver cp210x
usbserial: USB Serial support registered for cp210x
usbcore: registered new interface driver ftdi_sio
usbserial: USB Serial support registered for FTDI USB Serial Device
usbcore: registered new interface driver pl2303
usbserial: USB Serial support registered for pl2303

you should compare this one. and connect/remove/connect one time usb stick after booting was finished (best case in both design)
br
John
94
Open source hardware / How can i program with K150 isp
« Last post by fedekr on August 30, 2022, 04:12:29 PM »
Hello everybody.
is the first post I write on the forum.
I am trying to use a k150 board that I bought on the internet to program pic (pic16f73) but I have found few tutorials on the internet and apart from the fact that I still have problems writing the code and compiling it on mplab the microbrn program
when I do> program or> verify (I loaded a HEX file but empty for the moment it gives me all 3FF, but it gives me the error "the board is not responding, about to apply reset" and then "reset failed, please check" .

I can't understand what I have to do, I program with arduino and I didn't think it was so complicated, can you help me?


I'm not even sure if I should use the box or the six pins to the right of the board sorry for the ignorance ...


I can't figure out what to do if you want to help me I'll give you any information ...
95
Hey John,

thanks for your answer and the further Questions!

Quote
You use your own xsa from your vivado projects, correct? [...] When you use the same xsa, maybe your linux is not configured correctly.

Yes, I use the xsa archives from my own two different Vivado projects. Each Vivado project is based on the designated Trenz Board Files for the specific variant (The version of my Board Files for the EV differs from the version of the current Trenz reference Design. Mines were older, see below for my next try).
Each of the xsa archives is passed to Yocto and selected for the different MACHINEs in Yocto.


Quote
Why did you not use MIO?

I don't use the MIOs for MDIO, because there were no more free MIO Pins available (The PCB with the Ethernet Port is an extention to our existing carrier board, which provides a mix of PS and PL Pins on a B2B-Connector for future adaption,which we now used).

Quote
this is from 01 to 02 and you has 03 revision now

Thank you for remembering me. I also read this article before, but forgot to mention it in the post. The memory obviously changed, which might cause the error in combination with my ouddatetd board files (see below).

Thanks for mentioning the Trenz Reference Design. I downloaded and created the project for device number 63 (TE0803-03-5DI21-A). The Memory Settings are the same, but the board file version used in the reference design is newer compared to mine.

I created a new Vivado project based on the same board files as the reference design, then I went through the whole Yocto workflow again.
All in all that didn't help. The problem is still the same. (See attached Boot log)

Quote
Can you check also if  uboot recognise your eth phy on the carrier?

In both cases (CG and EV) U-Boot does not recognise the PHY. The U-Boot tools mii and mdio both do not see it. Nevertheless in the CG Case the Phy works after that in Linux and I can read the registers with Phytool. In case of the EV I can not read them. (See the attached screenshots)

I will now try to use as much of the working CG project for the EV Design.
Perhaps the point in time when the PHY reset occurs is slightly different and may cause the difference.
I will use the board files from the Reference Design for that.

I will also be in holiday next week and I might need a license renewal to create the bitstream for this new project, so please excuse a late feedback from my side.
I will let you know how it goes as soon as possible.

Daniel
96
Trenz Electronic FPGA Modules / Re: Linux USB problems with TE0720-03-2IF on TE0701
« Last post by OK on August 30, 2022, 08:52:15 AM »
Yes, these settings are enabled.

Here is the boot log captured via UART:

Code: [Select]
--------------------------------------------------------------------------------
Xilinx First Stage Boot Loader (TE modified)

Release 2019.1 Aug 25 2022-12:45:12

Device IDCODE: 23727093
Device Name: 7z020 (7)
Device Revision: 2
--------------------------------------------------------------------------------
TE0720 TE_FsblHookBeforeHandoff_Custom


SoM: TE0720-03-1C  F SC REV:05

MAC: 54 10 EC E1 D0 BF


--------------------------------------------------------------------------------


U-Boot 2019.01 (Aug 29 2022 - 11:52:56 +0000) Xilinx Zynq ZC702

CPU:   Zynq 7z020
Silicon: v3.1
DRAM:  ECC disabled 1 GiB
MMC:   mmc@e0100000: 0, mmc@e0101000: 1
In:    serial@e0000000
Out:   serial@e0000000
Err:   serial@e0000000
Net:   ZYNQ GEM: e000b000, phyaddr 0, interface rgmii-id
eth0: ethernet@e000b000
U-BOOT for petalinux
importing env from FSBL shared area at 0xFFFFFC00
Found valid magic
## Info: input data size = 27 = 0x1B

Hit any key to stop autoboot:  4  3  2  1  0
Device: mmc@e0100000
Manufacturer ID: 74
OEM: 4a60
Name: USDU1
Bus Speed: 50000000
Mode : SD High Speed (50MHz)
Rd Block Len: 512
SD version 3.0
High Capacity: Yes
Capacity: 29.4 GiB
Bus Width: 4-bit
Erase Group Size: 512 Bytes
4308592 bytes read in 255 ms (16.1 MiB/s)
## Loading kernel from FIT Image at 10000000 ...
   Using 'conf@system-top.dtb' configuration
   Verifying Hash Integrity ... OK
   Trying 'kernel@1' kernel subimage
     Description:  Linux kernel
     Type:         Kernel Image
     Compression:  uncompressed
     Data Start:   0x100000f4
     Data Size:    4288192 Bytes = 4.1 MiB
     Architecture: ARM
     OS:           Linux
     Load Address: 0x00008000
     Entry Point:  0x00008000
     Hash algo:    sha1
     Hash value:   6f7253bf1c8fcf4ac3243439df769b2624b841eb
   Verifying Hash Integrity ... sha1+ OK
## Loading fdt from FIT Image at 10000000 ...
   Using 'conf@system-top.dtb' configuration
   Verifying Hash Integrity ... OK
   Trying 'fdt@system-top.dtb' fdt subimage
     Description:  Flattened Device Tree blob
     Type:         Flat Device Tree
     Compression:  uncompressed
     Data Start:   0x104170b4
     Data Size:    18508 Bytes = 18.1 KiB
     Architecture: ARM
     Hash algo:    sha1
     Hash value:   21dc2cf238c94c27ec5449b10cd5cfbd2fff54ab
   Verifying Hash Integrity ... sha1+ OK
   Booting using the fdt blob at 0x104170b4
   Loading Kernel Image ... OK
   Loading Device Tree to 07ff8000, end 07fff84b ... OK

Starting kernel ...

Booting Linux on physical CPU 0x0
Linux version 4.14.0-xilinx (oe-user@oe-host) (gcc version 8.2.0 (GCC)) #1 SMP PREEMPT Mon Aug 29 12:32:37 UTC 2022
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
OF: fdt: Machine model: xlnx,zynq-7000
Memory policy: Data cache writealloc
cma: Reserved 128 MiB at 0x38000000
random: fast init done
percpu: Embedded 16 pages/cpu @ef7cc000 s34764 r8192 d22580 u65536
Built 1 zonelists, mobility grouping on.  Total pages: 260608
Kernel command line: console=ttyPS0,115200n8 earlyprintk root=/dev/mmcblk0p2 rw rootfstype=ext4
PID hash table entries: 4096 (order: 2, 16384 bytes)
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 897156K/1048576K available (6144K kernel code, 248K rwdata, 1892K rodata, 1024K init, 152K bss, 20348K reserved, 131072K cma-reserved, 131072K highmem)
Virtual kernel memory layout:
    vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
    vmalloc : 0xf0800000 - 0xff800000   ( 240 MB)
    lowmem  : 0xc0000000 - 0xf0000000   ( 768 MB)
    pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
    modules : 0xbf000000 - 0xbfe00000   (  14 MB)
      .text : 0xc0008000 - 0xc0700000   (7136 kB)
      .init : 0xc0a00000 - 0xc0b00000   (1024 kB)
      .data : 0xc0b00000 - 0xc0b3e300   ( 249 kB)
       .bss : 0xc0b3e300 - 0xc0b644c4   ( 153 kB)
Preemptible hierarchical RCU implementation.
RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
Tasks RCU enabled.
RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
efuse mapped to f0800000
slcr mapped to f0802000
L2C: platform modifies aux control register: 0x72360000 -> 0x72760000
L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000
L2C-310 erratum 769419 enabled
L2C-310 enabling early BRESP for Cortex-A9
L2C-310 full line of zeros enabled for Cortex-A9
L2C-310 ID prefetch enabled, offset 1 lines
L2C-310 dynamic clock gating enabled, standby mode enabled
L2C-310 cache controller enabled, 8 ways, 512 kB
L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001
zynq_clock_init: clkc starts at f0802100
Zynq clock init
sched_clock: 64 bits at 333MHz, resolution 3ns, wraps every 4398046511103ns
clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x4ce07af025, max_idle_ns: 440795209040 ns
Switching to timer-based delay loop, resolution 3ns
clocksource: ttc_clocksource: mask: 0xffff max_cycles: 0xffff, max_idle_ns: 537538477 ns
timer #0 at f080a000, irq=17
Console: colour dummy device 80x30
Calibrating delay loop (skipped), value calculated using timer frequency.. 666.66 BogoMIPS (lpj=3333333)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
CPU: Testing write buffer coherency: ok
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x100000 - 0x100060
Hierarchical SRCU implementation.
smp: Bringing up secondary CPUs ...
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
smp: Brought up 1 node, 2 CPUs
SMP: Total of 2 processors activated (1333.33 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
futex hash table entries: 512 (order: 3, 32768 bytes)
pinctrl core: initialized pinctrl subsystem
NET: Registered protocol family 16
DMA: preallocated 256 KiB pool for atomic coherent allocations
cpuidle: using governor menu
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
zynq-ocm f800c000.ocmc: ZYNQ OCM pool: 256 KiB @ 0xf0880000
zynq-pinctrl 700.pinctrl: zynq pinctrl initialized
e0000000.serial: ttyPS0 at MMIO 0xe0000000 (irq = 27, base_baud = 6249999) is a xuartps
console [ttyPS0] enabled
e0001000.serial: ttyPS1 at MMIO 0xe0001000 (irq = 28, base_baud = 6249999) is a xuartps
vgaarb: loaded
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
media: Linux media interface: v0.10
Linux video capture interface: v2.00
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
PTP clock support registered
EDAC MC: Ver: 3.0.0
FPGA manager framework
fpga-region fpga-full: FPGA Region probed
Advanced Linux Sound Architecture Driver Initialized.
clocksource: Switched to clocksource arm_global_timer
NET: Registered protocol family 2
TCP established hash table entries: 8192 (order: 3, 32768 bytes)
TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
TCP: Hash tables configured (established 8192 bind 8192)
UDP hash table entries: 512 (order: 2, 16384 bytes)
UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
hw perfevents: no interrupt-affinity property for /pmu@f8891000, guessing.
hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available
workingset: timestamp_bits=30 max_order=18 bucket_order=0
jffs2: version 2.2. (NAND) (SUMMARY)  © 2001-2006 Red Hat, Inc.
bounce: pool size: 64 pages
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
io scheduler mq-deadline registered
io scheduler kyber registered
dma-pl330 f8003000.dmac: Loaded driver for PL330 DMAC-241330
dma-pl330 f8003000.dmac: DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Events-16
brd: module loaded
loop: module loaded
m25p80 spi0.0: s25fl256s1 (32768 Kbytes)
4 ofpart partitions found on MTD device spi0.0
Creating 4 MTD partitions on "spi0.0":
0x000000000000-0x000000500000 : "boot"
0x000000500000-0x000000520000 : "bootenv"
0x000000520000-0x000000fa0000 : "kernel"
0x000000fa0000-0x000002000000 : "spare"
libphy: Fixed MDIO Bus: probed
CAN device driver interface
libphy: MACB_mii_bus: probed
[Firmware Warn]: /amba/ethernet@e000b000/ethernet-phy@0: Whitelisted compatible string. Please remove
macb e000b000.ethernet eth0: Cadence GEM rev 0x00020118 at 0xe000b000 irq 32 (54:10:ec:e1:d0:bf)
Marvell 88E1510 e000b000.ethernet-ffffffff:00: attached PHY driver [Marvell 88E1510] (mii_bus:phy_addr=e000b000.ethernet-ffffffff:00, irq=POLL)
e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k
e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
ehci-pci: EHCI PCI platform driver
ehci-platform: EHCI generic platform driver
usbcore: registered new interface driver uas
usbcore: registered new interface driver usb-storage
usbcore: registered new interface driver usbserial
usbcore: registered new interface driver usbserial_generic
usbserial: USB Serial support registered for generic
usbcore: registered new interface driver cp210x
usbserial: USB Serial support registered for cp210x
usbcore: registered new interface driver ftdi_sio
usbserial: USB Serial support registered for FTDI USB Serial Device
usbcore: registered new interface driver pl2303
usbserial: USB Serial support registered for pl2303
i2c /dev entries driver
cdns-i2c e0004000.i2c: 400 kHz mmio e0004000 irq 23
rtc-isl12022 1-006f: rtc core: registered rtc-isl12022 as rtc0
cdns-i2c e0005000.i2c: 400 kHz mmio e0005000 irq 24
IR NEC protocol handler initialized
IR RC5(x/sz) protocol handler initialized
IR RC6 protocol handler initialized
IR JVC protocol handler initialized
IR Sony protocol handler initialized
IR SANYO protocol handler initialized
IR Sharp protocol handler initialized
IR MCE Keyboard/mouse protocol handler initialized
IR XMP protocol handler initialized
cdns-wdt f8005000.watchdog: Xilinx Watchdog Timer at f092c000 with timeout 10s
EDAC MC: ECC not enabled
Xilinx Zynq CpuIdle Driver started
sdhci: Secure Digital Host Controller Interface driver
sdhci: Copyright(c) Pierre Ossman
sdhci-pltfm: SDHCI platform and OF driver helper
mmc0: SDHCI controller on e0100000.mmc [e0100000.mmc] using ADMA
mmc0: new high speed SDHC card at address 59b4
mmcblk0: mmc0:59b4 USDU1 29.4 GiB
 mmcblk0: p1 p2
mmc1: SDHCI controller on e0101000.mmc [e0101000.mmc] using ADMA
ledtrig-cpu: registered to indicate activity on CPUs
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
ad9467_fftwindow 40000000.cf-dlr-axi-fftwindow: AD9467 FFT Window engine probed.
ad_dummy_adc amba:cf-avg-adcdummy-core-lpc: Dummy ADC reports 0 on probing
ad_dummy_adc amba:cf-avg-adcdummy-core-lpc: Dummy ADC probed. Yay!
mmc1: new high speed MMC card at address 0001
mmcblk1: mmc1:0001 Q2J54A 3.59 GiB
ad9517 spi1.1: AD9517 successfully initialized
fpga_manager fpga0: Xilinx Zynq FPGA Manager registered
NET: Registered protocol family 10
Segment Routing with IPv6
sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
NET: Registered protocol family 17
can: controller area network core (rev 20170425 abi 9)
NET: Registered protocol family 29
can: raw protocol (rev 20170425)
can: broadcast manager protocol (rev 20170425 t)
can: netlink gateway (rev 20170425) max_hops=1
Registering SWP/SWPB emulation handler
mmcblk1boot0: mmc1:0001 Q2J54A partition 1 16.0 MiB
mmcblk1boot1: mmc1:0001 Q2J54A partition 2 16.0 MiB
mmcblk1rpmb: mmc1:0001 Q2J54A partition 3 512 KiB
 mmcblk1:
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  IDELAY 0x1
cf_axi_adc 44a00000.axi_ad9467: ADI AIM (10.01.b) at 0x44A00000 mapped to 0xf09e0000, probed ADC AD9467 as MASTER
rtc-isl12022 1-006f: setting system clock to 2022-08-25 16:51:38 UTC (1661446298)
of_cfs_init
of_cfs_init: OK
ALSA device list:
  No soundcards found.
EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null)
VFS: Mounted root (ext4 filesystem) on device 179:2.
devtmpfs: mounted
Freeing unused kernel memory: 1024K

INIT: version 2.88 booting

Starting udev
udevd[823]: starting version 3.2.5
udevd[824]: starting eudev-3.2.5
FAT-fs (mmcblk0p1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.
EXT4-fs (mmcblk0p2): re-mounted. Opts: (null)
 Starting iiod


INIT: Entering runlevel: 5


Configuring network interfaces... IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
Error: Nexthop has invalid gateway.

Starting system message bus: dbus.

Starting Dropbear SSH server: dropbear.

starting Busybox HTTP Daemon: httpd... done.

Starting internet superserver: inetd.

Starting syslogd/klogd: done

Starting tcf-agent: OK


PetaLinux 2019.1 daqlinux /dev/ttyPS0



daqlinux login: macb e000b000.ethernet eth0: link up (1000/Full)
IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready

97
Trenz Electronic FPGA Modules / Re: Linux USB problems with TE0720-03-2IF on TE0701
« Last post by JH on August 30, 2022, 08:27:13 AM »
Hi,
did you checked, if these settings are enabled on your kernel:
https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842272/Zynq+Linux+USB+Device+Driver#ZynqLinuxUSBDeviceDriver-HostMode

can you share your whole boot log?

br
John
98
Trenz Electronic FPGA Modules / Re: Linux USB problems with TE0720-03-2IF on TE0701
« Last post by OK on August 30, 2022, 07:53:27 AM »
Thanks.

I have your devicetree entries. I'm wondering if the usb reset pin has to be configured. If I see it correctly the USB reset is done via the FSBL which is in turn piped through the CPLD (from the schematics...). Does the linux kernel also has to toggle the reset pin (and if yes which GPIO/MIO Pin does that correspond to?)? I think the problem ist that the EHCI device is never discovered/probed by the kernel. I see a bunch of USB drivers (and also usbfs) loaded in dmesg but it seems the EHCI is never discovered. In the u-boot console everything works fine and the EHCI is working just fine (attached devices are also correctly indentified).
99
Trenz Electronic FPGA Modules / Re: Linux USB problems with TE0720-03-2IF on TE0701
« Last post by JH on August 29, 2022, 01:31:10 PM »
Hi,
check device tree. Unfortunately we document only changes which we must do manually (default device tree and changes from xilinx during xsa import are not included into our documentation):
https://wiki.trenz-electronic.de/display/PD/TE0720+Test+Board#TE0720TestBoard-DeviceTree
For kernel we did not change anything which is related to USB...it's Xilinx default

Xilinx has some documentation here:
https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842272/Zynq+Linux+USB+Device+Driver
or you check Xilinx device tree git:
https://wiki.trenz-electronic.de/display/PD/PetaLinux+KICKstart#PetaLinuxKICKstart-References

PS: Xilinx Linux kernel is changed very often...see Xilinx petalinux release notes from different petalinux versions, we have some links here:
https://wiki.trenz-electronic.de/display/PD/Xilinx+Development+Tools#XilinxDevelopmentTools-XilinxSoftware-ProductUpdateReleaseNotesandKnownIssues

br
John
100
Trenz Electronic FPGA Modules / Re: Linux USB problems with TE0720-03-2IF on TE0701
« Last post by OK on August 29, 2022, 12:49:57 PM »
Yes, I have tested that and It works fine. As I would expect...

How to proceed? My deviations from test board are as following:
  • U-Boot --> Should be the same, the platform-top.h change is applied by petalinux
  • FSBL --> Should be the same, I have integrated the TE hooks as a patch
  • Bitstream --> Different but is based on the Test Board Design
  • Linux Kernel --> Completely different as it is the Xilinx linux kernel modified by Analog Devices and modified by me with additional custom drivers for IP Cores

I still suspect the kernel/kernel config to be an issue, I just don't know where to start/look for details.
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