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#81
Trenz Electronic FPGA Modules / Re: S7Mini program flash
Last post by salmawisoky - November 20, 2023, 06:08:04 AMTo load the flash of S7Mini using a TCL script, you can follow these steps:
1. Generate the bitstream file: Use Vivado to generate the bitstream file (.bit) for your design using the "write_bitstream" command. Make sure to include the necessary configuration options for the Spartan-7 FPGA on the S7Mini board.
2. Select the flash device: In Vivado, you need to select the appropriate flash device for programming. The n25q64-3.3v-spi-x1_x2_x4 is a common flash device used in many boards. You can confirm if this is the correct flash device for your S7Mini board by referring to the board's documentation or specifications.
3. Generate a programming file: To load the bitstream into the flash, you need to generate a programming file (.mcs or .bin) that combines the bitstream with the necessary configuration data for the flash device. This file defines the format and contents to be written to the flash memory.
4. Use the TCL script: Write a TCL script that automates the programming process. Within the script, you can use the Vivado TCL commands to specify the flash device, load the bitstream file, and generate the programming file.
Here's an example of the TCL script to load the flash:
```
# Set the flash device
set_property PROGRAM.BLANK_CHECK 0 [get_mfg_parts "n25q64-3.3v-spi-x1_x2_x4"]
# Load the bitstream
set_property BITSTREAM.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR NO [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 33MHZ [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DIV-2 [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
# Generate the programming file
write_cfgmem -force -format MCS -size 16 -interface SPIx4 -loadbit "up 0x0 <bitstream_file.bit>" -file "output_file.mcs"
```
Replace `<bitstream_file.bit>` with the path to your generated bitstream file. The script sets the flash device properties, configures the bitstream settings, and generates the programming file in MCS format.
Make sure to customize the script based on your specific configuration and flash device requirements. You can execute the TCL script within the Vivado TCL console or run it using the Vivado batch mode.
Remember to refer to the Vivado documentation and the S7Mini board documentation for detailed information on flash programming and configuration settings specific to your board.
1. Generate the bitstream file: Use Vivado to generate the bitstream file (.bit) for your design using the "write_bitstream" command. Make sure to include the necessary configuration options for the Spartan-7 FPGA on the S7Mini board.
2. Select the flash device: In Vivado, you need to select the appropriate flash device for programming. The n25q64-3.3v-spi-x1_x2_x4 is a common flash device used in many boards. You can confirm if this is the correct flash device for your S7Mini board by referring to the board's documentation or specifications.
3. Generate a programming file: To load the bitstream into the flash, you need to generate a programming file (.mcs or .bin) that combines the bitstream with the necessary configuration data for the flash device. This file defines the format and contents to be written to the flash memory.
4. Use the TCL script: Write a TCL script that automates the programming process. Within the script, you can use the Vivado TCL commands to specify the flash device, load the bitstream file, and generate the programming file.
Here's an example of the TCL script to load the flash:
```
# Set the flash device
set_property PROGRAM.BLANK_CHECK 0 [get_mfg_parts "n25q64-3.3v-spi-x1_x2_x4"]
# Load the bitstream
set_property BITSTREAM.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR NO [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 33MHZ [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DIV-2 [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
# Generate the programming file
write_cfgmem -force -format MCS -size 16 -interface SPIx4 -loadbit "up 0x0 <bitstream_file.bit>" -file "output_file.mcs"
```
Replace `<bitstream_file.bit>` with the path to your generated bitstream file. The script sets the flash device properties, configures the bitstream settings, and generates the programming file in MCS format.
Make sure to customize the script based on your specific configuration and flash device requirements. You can execute the TCL script within the Vivado TCL console or run it using the Vivado batch mode.
Remember to refer to the Vivado documentation and the S7Mini board documentation for detailed information on flash programming and configuration settings specific to your board.
#82
UltraScale / TE0820 POR with JTAG TE0790
Last post by pema - November 17, 2023, 09:12:50 AMHi there,
Question: How to POR the TE820 after flashing it, without physical interaction?
Problem Description: Every time after flashing the TE820 eMMC I need to perform a POR over the RESIN signal line (Connector JM2 Pin 18). This can be either over the push button on the Carrier board or with a full power reset.
I have tried already all kinds of reset over the XSCT but none of them seems to work. So I normally, just have one of those cheap wifi power plugs connected to the TE820 to perform a POR( by power OFF power ON).
Is there any other way to perform this without needing to press the Push button or Power boot? Perhaps a signal line from the TE0790 to perform the POR ? ( I could solder a wire to the Carrier board) XMOD E and XMOD G are still free. Would it be possible to provide the code to the CPLD in the TE0790 or modify it in order to provide a SRST signal over XSCT?
Many Thanks and have a nice weekend .
Question: How to POR the TE820 after flashing it, without physical interaction?
Problem Description: Every time after flashing the TE820 eMMC I need to perform a POR over the RESIN signal line (Connector JM2 Pin 18). This can be either over the push button on the Carrier board or with a full power reset.
I have tried already all kinds of reset over the XSCT but none of them seems to work. So I normally, just have one of those cheap wifi power plugs connected to the TE820 to perform a POR( by power OFF power ON).
Is there any other way to perform this without needing to press the Push button or Power boot? Perhaps a signal line from the TE0790 to perform the POR ? ( I could solder a wire to the Carrier board) XMOD E and XMOD G are still free. Would it be possible to provide the code to the CPLD in the TE0790 or modify it in order to provide a SRST signal over XSCT?
Many Thanks and have a nice weekend .
#83
UltraScale / Reference Design & Custom Usag...
Last post by jwil - November 16, 2023, 08:17:36 PMHello, I am in the process of bringing up the 2022.2 Reference Design for the TE0818 SOM +TEBF0818 Carrier. I would like to know more about the default configuration of the SI5345 that is onboard the TE0818 SOM. I have located the associated SkyWorks SI5345 slabtimeproj file in the reference design and have viewed it in ClockBuilderPro.
Is there documentation or a breakdown of how each output port is being used by the SOM under the provided project?
Are there input and output ports specifically left unused for designs to source / consume from off-board? If so, how many, and which ones?
Any other pointers to consider regarding use of the onboard SI5345 are welcome.
Thanks in advance.
Is there documentation or a breakdown of how each output port is being used by the SOM under the provided project?
Are there input and output ports specifically left unused for designs to source / consume from off-board? If so, how many, and which ones?
Any other pointers to consider regarding use of the onboard SI5345 are welcome.
Thanks in advance.
#84
Trenz Electronic FPGA Modules / Re: TE0890 - Power Consumption...
Last post by Vadim Y - November 16, 2023, 10:15:01 AMHello cjc220,
The TE0890 contains no control signals that could disable unused power supplies or delay FPGA configuration.
In the old datasheet of HyperRam U2 there is a note that in Power On Reset mode it consume about 50mA. I would recommend to pull the signal CS0 high to turn off the IC.
https://www.issi.com/WW/pdf/66-67WVH8M8ALL-BLL.pdf
Best regards,
Vadim
The TE0890 contains no control signals that could disable unused power supplies or delay FPGA configuration.
In the old datasheet of HyperRam U2 there is a note that in Power On Reset mode it consume about 50mA. I would recommend to pull the signal CS0 high to turn off the IC.
https://www.issi.com/WW/pdf/66-67WVH8M8ALL-BLL.pdf
Best regards,
Vadim
#85
UltraScale / Re: Upgrade Toolchain 2019.2 t...
Last post by evawillms - November 10, 2023, 03:44:13 AMQuote from: JH on November 04, 2022, 08:46:33 AMWhich was working fine.Thank so much.
Hi,
can you try out our 21.2 template with our prebuilt xsa files, this should works:
https://wiki.trenz-electronic.de/display/PD/TE0808+StarterKit Run 3
Template project is in:
https://wiki.trenz-electronic.de/display/PD/TE0808+StarterKit#TE0808StarterKit-DesignSources
copy xsa from prebuilt folder to the petalinux folder and start with point 3 "petalinux-config --get-hw-description"
https://wiki.trenz-electronic.de/display/PD/PetaLinux+KICKstart#PetaLinuxKICKstart-CreatingaProjectfromVivadoProject
in case this doesn't work, check your build environment.
https://wiki.trenz-electronic.de/display/PD/PetaLinux+KICKstart#PetaLinuxKICKstart-PetaLinuxInstallation
I use Ubuntu 20.4 on WSL which was working fine.
br
John
#86
Trenz Electronic FPGA Modules / TE0890 - Power Consumption
Last post by cjc220 - November 04, 2023, 12:43:38 PMHi,
I am relatively new to using FPGA modules and have a potentially basic question regarding the typical power consumption of FPGA boards in an idle state. I am using the TE0890 and the idle power consumption seems to be around 100mA when supplying 5V to the board. This is when the board has not yet been programmed, so everything should be completely idle. This seems quite high as someone who has previously worked with low-power microcontrollers.
After programming the board's flash memory, the current draw on the 5V line drops to approximately 65mA. Following a power cycle, the chip then reads the flash ROM and starts up. Whilst reading the ROM the current is roughly 100mA, this then jumps to roughly 130mA when running the 'Hello World' reference design.
Is there any way to reduce the idle power consumption of this board? I am planning to use this board for a battery powered application so any reduction in power consumption is helpful. Is there a reason that the current drops by 35mA after the ROM has been programmed - is something (i.e., flash memory, FPGA core itself) being switched off?
Thanks in advance for any help.
I am relatively new to using FPGA modules and have a potentially basic question regarding the typical power consumption of FPGA boards in an idle state. I am using the TE0890 and the idle power consumption seems to be around 100mA when supplying 5V to the board. This is when the board has not yet been programmed, so everything should be completely idle. This seems quite high as someone who has previously worked with low-power microcontrollers.
After programming the board's flash memory, the current draw on the 5V line drops to approximately 65mA. Following a power cycle, the chip then reads the flash ROM and starts up. Whilst reading the ROM the current is roughly 100mA, this then jumps to roughly 130mA when running the 'Hello World' reference design.
Is there any way to reduce the idle power consumption of this board? I am planning to use this board for a battery powered application so any reduction in power consumption is helpful. Is there a reason that the current drops by 35mA after the ROM has been programmed - is something (i.e., flash memory, FPGA core itself) being switched off?
Thanks in advance for any help.
#87
Trenz Electronic FPGA Modules / Re: Petalinux-package, unsuppo...
Last post by JH - October 25, 2023, 04:22:20 PMHi,
as I know Eval License did not include bitfile generation. And on installation step, you must add device families which should be installed. not all are selected automatically.
br
John
as I know Eval License did not include bitfile generation. And on installation step, you must add device families which should be installed. not all are selected automatically.
br
John
#88
Trenz Electronic FPGA Modules / Re: Petalinux-package, unsuppo...
Last post by embedded.kyle - October 25, 2023, 03:28:57 PMI have installed a 30 day evaluation of the Enterprise license. However, when I went to check that this was installed correctly by opening the GUI, I've just been using command line tools up to this point) I get the an error trying to open the Trenz Electronic reference design project (see attached).
I can open and synthesize the TE reference design project on Windows. However, PetaLinux tooling requires Linux to run. So I've set up a WSL environment for PetaLinux and also installed Vivado there as well. However, in the WSL run Vivado, the KU040 part is not available. I am not sure why this is and cannot find instructions on how to update the part database.
Do you have instructions on how to update the Vivado parts list to include the parts you use on your boards? Do you have instructions on creating the MCS file from Vivado?
I can open and synthesize the TE reference design project on Windows. However, PetaLinux tooling requires Linux to run. So I've set up a WSL environment for PetaLinux and also installed Vivado there as well. However, in the WSL run Vivado, the KU040 part is not available. I am not sure why this is and cannot find instructions on how to update the part database.
Do you have instructions on how to update the Vivado parts list to include the parts you use on your boards? Do you have instructions on creating the MCS file from Vivado?
#89
Trenz Electronic FPGA Modules / Re: TE0820 Custom Carrier Disp...
Last post by George - October 25, 2023, 11:35:51 AMIf the DPAUX signals are originally at 3.3V and the carrier board operates with 1.8V MIO (Multiplexed I/O) voltage, using a level shifter is indeed a suitable approach to ensure proper voltage translation. The SN74A series level shifters, which are specifically designed for voltage level conversion, can be a suitable choice for this purpose.
Regarding the resistors (R40, R41) on the HPD (Hot Plug Detect) signal, their presence or removal depends on the specific design and requirements of the system. These resistors are often used for managing the hot-plug detection functionality. If you are modifying the design, it's advisable to consult the relevant documentation or consult with the manufacturer to understand the purpose of these resistors and whether they should be removed or kept in your specific configuration.
Regarding the resistors (R40, R41) on the HPD (Hot Plug Detect) signal, their presence or removal depends on the specific design and requirements of the system. These resistors are often used for managing the hot-plug detection functionality. If you are modifying the design, it's advisable to consult the relevant documentation or consult with the manufacturer to understand the purpose of these resistors and whether they should be removed or kept in your specific configuration.
#90
Trenz Electronic FPGA Modules / Re: Petalinux Build [Errno 32]...
Last post by Calista - October 25, 2023, 10:53:40 AMI want to ask about how to upgrade to the latest updates. Does it cause any effects?