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21
Trenz Electronic FPGA Modules / Re: TE7012 PetaLinux Ethernet problem
« Last post by matix on October 27, 2022, 01:04:50 PM »
Thanks for your replay.
I have TE0712-02-82I36-A(XC7A200T-2FBG282l) with TE0701-06 carrier board.

I have tried reference designs from trenz 2021.2 and older.
Lastly I have flashed 2017.4 version and observed that some packets were sent, only UDP. But TCP still does not work, I'am not able to ping to board and from board.
22
Trenz Electronic FPGA Modules / Re: TE7012 PetaLinux Ethernet problem
« Last post by Waldi3141 on October 27, 2022, 10:34:31 AM »
Hi Matix,

i tried to replicate your problem but couldn't. Ethernet worked without problems. I used the TE0712 rev 01 and the Carrier TE0701 rev04. On the TE0712 i used the test_board design version 2021.2
Can you tell me what Module and carrier exactly you use? like TE0712-02-35-2I
Also what reference design did you try?
Please try with the latest version 2021.2

best regards

Waldi
23
Hi John,

The difference I found in the Kernel Configuration was about the Xilinx_APF and XILINX_DMA_APF Configs.
These were not activated so far and I expected that the DMA Problem with the Ethernet Port may disappear, when these Configs are activated again.

Unfortunately this did not help.
The Ethernet Port still only works, if I set 2GB of memory in Vivado instead of 4GB.

Even if I don't understand the reason for that, I am okay with it for now.

Thanks for all your replies and Questions!
Daniel
24
One addition from my side:

I just find a diffrence in the two kernel configurations.
I will try a 4GB Design with the same kernel configuration from the CG and will let you now, if the EV works with 4GB and the Phy after that.

Best Regards
Daniel
25
Hi,

sorry for my delayed answer...

I now managed to bring up the PHY with the EV variant.
While comparing my CG Vivado project and my EV Vivado project the RAM settings were the only major difference.

The PHY works with the EV, when I change the RAM settings in Vivado from 4GB, which is the default set by the EV Board Files, to 2GB only.
The devicetree generated by the Xilinx Devicetree Generator during the Yocto build is changing accordingly (See attached screenshots).

In both working Cases (CG and EV) U-Boot tells
Code: [Select]
Net:   MDIO bus not found ethernet@ff0b0000
No ethernet found.

during boot.

Nevertheless the PHY is working fine after the kernel is bootet and I can also read the PHY Registers with phytool.

I checked all the address spaces for the GEM0, 2GB and 4GB memory from the devicetree from the reg properties. The addresses of the memory and the GEM0 do not collide.
The 4GB memory variant uses 2 Blocks of 2GB, one from 0x0 to 0x7ff0000 and one from 0x800000000 to 0x880000000.
The address space of GEM0 lies in between these two blocks, but does not collide (0xff0b0000 to 0xff0b1000).

Do you have any idea or comment on this?

Many thanks!
Daniel
26
Trenz Electronic FPGA Modules / Re: TE720 QSPI boot corrupting
« Last post by JH on October 20, 2022, 07:00:27 AM »
Hi,
I have never heard of such a issue. For eMMC yes(if they don't shutdown properly, it can happen, that emmc is corrupted), but never from QSPI. Do you read/write something to the QSPI Flash with your design?. You could run our prebuilt Linux from the reference design and see if you can reproduce this issue? I know it's hard to find out what's happens, when I hear it appears very rarely.
br
John
27
Trenz Electronic FPGA Modules / TE720 QSPI boot corrupting
« Last post by akarcher on October 19, 2022, 11:20:05 PM »
I have moved a working design from SD-card boot and rootfs to boot from QSPI with image.ub on the boot partition of the eMMC, Rootfs on an ext4 partition of eMMC. This works very well. However at rare and random intervals (~ once a month) the QSPI gets corrupted and I have to re-flash the boot.bin to QSPI to be able to boot. I have no idea how this could happen. Any input would be appreciated. Since this happens so rarely I don't know how to debug this effectively. Since the rootfs is not effected all log files are still present.
28
Trenz Electronic FPGA Modules / TE7012 PetaLinux Ethernet problem
« Last post by matix on October 19, 2022, 04:13:06 PM »
Hello,

I have TE0712 FPGA module, on TE0701 carrier board. My problem is that I'm not able to get Ethernet working. My booting process is from Flash memory, where i place .MCS file. I've tested reference design files as well as my own design but problem is always the same. Message from linux boot-up process is "eth0: Exceeded transmit timeout of 6000 ms".  I have checked clocks on Si5338 chip and it's 50MHz on output as supposed to be. Attached screen-shots below.


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Quote
I'm guessing this may be a qSPI  initialization or a power-up latency problem ?
but why only on secured boot?
Can you hold reset button during power up and release later? In this case  you should simple add more delay.
Quote
Since the BOOTROM searches the qSPI for a valid boot image, I just flashed the image at a higher address (0x8000) in the qSPI and now it boots securely from the qSPI
hm strange, another idea is that with secured files the entry points are different and it does not recognize flash has a valid files...but only Xilinx can know that. At least you have a solution for now with the offset. Thanks to share this notes here.
br
John
30
Hi John, thanks for your input

The problem appears to be that the BOOTROM cannot read the first few words in the qSPI flash after POR / boot.

I'm guessing this may be a qSPI  initialization or a power-up latency problem ?

Since the BOOTROM searches the qSPI for a valid boot image, I just flashed the image at a higher address (0x8000) in the qSPI and now it boots securely from the qSPI

Thanks
Malc
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