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Trenz Electronic FPGA Modules / Re: TE0720 D5 LED behavior?
« Last post by JH on December 04, 2023, 07:22:46 AM »
TE0720 CPLD Description is here:
What's the status of the other 2 LEDs?

There is normally some problem in case it blinks.
If everything starts up correctly. LED5 can be controlled from user via MDIO interface, see:
Examples to get access are included into the documentation or our reference designs:

thanks John
Trenz Electronic FPGA Modules / TE0720 D5 LED behavior?
« Last post by AaronB on November 29, 2023, 05:43:50 PM »
I am currently booting petalinux using a TE0720 mounted on a custom board.  In my boot image, I have a firmware image that should be getting flashed by the first stage boot loader.  Everything seems like its working, so maybe this is a request for information.

Can someone tell me if this D5 LED is supposed to continue blinking forever?  This is what I am seeing, but for some reason, I thought it was supposed to stop blinking once the firmware was programmed.  I'm poking around in petalinux, and it looks like my firmware might be loaded.  However, I wonder if I did everything correctly.

the TRM only says this LED is controlled by the System Controller CPLD, without reference to its expected behavior.  I understand through experience and forum posts that it blinks quickly for QSPI boot and slowly for SD boot.  There are also forum references to 1/8 duty cycle blinking in some cases, though I don't think I've ever seen this.

I have seen forum links to a wiki page on trenz's website, but I don't appear to have access to that.  I get an Atlassian login page that doesn't appear to accept my credientials for
There are also a Minimig core in development, That suports AGA and uses the UnAMIGA branch.
This is an interactive bill of materials, nowadays the SD has 4bit mode and is not share with the 2x20 Raspberry pi port. But in the future i'm going to share the signals an put also in the 2x20 pi bus.
Nowadays also seeing the rp2040, to control the cores that were sintetized in the platform.

More info available here:
Trenz Electronic FPGA Modules / Re: TE0705 USB over-current signal routing
« Last post by JH on November 24, 2023, 12:37:54 PM »
Hi, you can only read it over I2C IP:

CPLD Source code is available on the download area of the TE0705, so you can change it like you want.
UltraScale / Re: TE0820 POR with JTAG TE0790
« Last post by pema on November 24, 2023, 11:21:18 AM »
Ok I got it. now. Thanks for clearing that up.  ;)
UltraScale / Re: TE0820 POR with JTAG TE0790
« Last post by JH on November 24, 2023, 10:42:09 AM »
Button goes directly to the 2.54 mm pinheader(so output from XMOD):
and to this pin(Input for CPLD). It simple xor LED so you can see that you press the button

Or see schematics and source code.

In case you didn't press button, than you can also use G as output or set G as tri state with pullup activated where you force only to GND, in this case you didn't get a electrical conflict when someone press the button.

UltraScale / Re: TE0820 POR with JTAG TE0790
« Last post by pema on November 24, 2023, 10:16:43 AM »
Hi John,
yes I realize that you cant know what AMD over the xsct/xsdb sends.
Can you please tell me what is the purpose from the  "Button (Reset_n)" on the JTAG TE0790 2x6 Pin Header ? Input? output?
UltraScale / Re: TE0820 POR with JTAG TE0790
« Last post by JH on November 23, 2023, 01:47:51 PM »
The signal from connector J2 pin G already gives this signal right ?. How is the signal activated from the xsct/xsdb?
that's not possible or much effort. xsct/sdb use JTAG for communication. JTAG is only one channel from FTDI(translate USB to JTAG) which is routed through the CPLD. CPLD is only Levelshifter with the advance that you can change Pinout from the 2,54mm pinheader if needed.

I can't tell you what AMD transmits and how, only AMD knows that.
Instead of HW Reset U+ Zynq has mechanism to reboot via JTAG, I think that's what AMD try when they say reboot.
But there are different depths of reboot possible, not all of them reset all registers and re-evaluate the boot mode again, so this does not always work

You can check if you find some mechanism from TRM:
And U+ Zynq register description:

or you create you custom carrier with microcontroller, which can force reset.

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