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#1
Trenz Electronic FPGA Modules / JFFS2 errors, QSPI data doesn'...
Last post by neels - April 22, 2024, 05:10:32 PMHi All,
I have a TE0720 module. I have a design that was running on a old Vivado toolchain (2016.2). I am currently updating the design to use Vivado 2021.2 toolchain. Much of the tool migration has gone as expected. But I have had a few issues with the QSPI on 2021.2 toolchain. I have the following patch that changes the QSPI from the default to my custom config.
The above patch used to work fine in the 2016.2 version (jffs2 had no errors, QSPI data used to persist after reboots). But on the 2021.2 version I am have noticed a lot of jffs2 errors in the boot log (as shown below) and the QSPI doesn't persist data after reboots.
From the log it can be seen that the MTD device is detected and the patches are taking effect. But the data on QSPI doesn't persist after the reboot.
I have attached a full log if it is of interest. Any pointers to fix the issue is greatly appreciated.
I have a TE0720 module. I have a design that was running on a old Vivado toolchain (2016.2). I am currently updating the design to use Vivado 2021.2 toolchain. Much of the tool migration has gone as expected. But I have had a few issues with the QSPI on 2021.2 toolchain. I have the following patch that changes the QSPI from the default to my custom config.
Code Select
--- project-spec/configs/config 2024-04-22 14:46:11.193697828 +0100
@@ -35,7 +35,7 @@
CONFIG_SUBSYSTEM_MEMORY_PS7_DDR_0_BANKLESS_SELECT=y
# CONFIG_SUBSYSTEM_MEMORY_MANUAL_SELECT is not set
CONFIG_SUBSYSTEM_MEMORY_PS7_DDR_0_BANKLESS_BASEADDR=0x0
-CONFIG_SUBSYSTEM_MEMORY_PS7_DDR_0_BANKLESS_SIZE=0x10000000
+CONFIG_SUBSYSTEM_MEMORY_PS7_DDR_0_BANKLESS_SIZE=0x0e000000
CONFIG_SUBSYSTEM_MEMORY_PS7_DDR_0_BANKLESS_KERNEL_BASEADDR=0x0
CONFIG_SUBSYSTEM_MEMORY_PS7_DDR_0_BANKLESS_U__BOOT_TEXTBASE_OFFSET=0x400000
CONFIG_SUBSYSTEM_MEMORY_IP_NAME="PS7_DDR_0"
@@ -43,12 +43,12 @@
#
# Serial Settings
#
-# CONFIG_SUBSYSTEM_FSBL_SERIAL_PS7_UART_0_SELECT is not set
-CONFIG_SUBSYSTEM_FSBL_SERIAL_PS7_UART_1_SELECT=y
+CONFIG_SUBSYSTEM_FSBL_SERIAL_PS7_UART_0_SELECT=y
+# CONFIG_SUBSYSTEM_FSBL_SERIAL_PS7_UART_1_SELECT is not set
# CONFIG_SUBSYSTEM_FSBL_SERIAL_AXI_UART16550_0_SELECT is not set
# CONFIG_SUBSYSTEM_FSBL_SERIAL_MANUAL_SELECT is not set
-# CONFIG_SUBSYSTEM_SERIAL_PS7_UART_0_SELECT is not set
-CONFIG_SUBSYSTEM_SERIAL_PS7_UART_1_SELECT=y
+CONFIG_SUBSYSTEM_SERIAL_PS7_UART_0_SELECT=y
+# CONFIG_SUBSYSTEM_SERIAL_PS7_UART_1_SELECT is not set
# CONFIG_SUBSYSTEM_SERIAL_AXI_UART16550_0_SELECT is not set
# CONFIG_SUBSYSTEM_SERIAL_MANUAL_SELECT is not set
# CONFIG_SUBSYSTEM_SERIAL_PS7_UART_0_BAUDRATE_600 is not set
@@ -72,8 +72,8 @@
# CONFIG_SUBSYSTEM_SERIAL_AXI_UART16550_0_BAUDRATE_230400 is not set
# CONFIG_SUBSYSTEM_SERIAL_AXI_UART16550_0_BAUDRATE_460800 is not set
# CONFIG_SUBSYSTEM_SERIAL_AXI_UART16550_0_BAUDRATE_921600 is not set
-CONFIG_SUBSYSTEM_SERIAL_FSBL_IP_NAME="ps7_uart_1"
-CONFIG_SUBSYSTEM_SERIAL_IP_NAME="ps7_uart_1"
+CONFIG_SUBSYSTEM_SERIAL_FSBL_IP_NAME="ps7_uart_0"
+CONFIG_SUBSYSTEM_SERIAL_IP_NAME="ps7_uart_0"
#
# Ethernet Settings
The above patch used to work fine in the 2016.2 version (jffs2 had no errors, QSPI data used to persist after reboots). But on the 2021.2 version I am have noticed a lot of jffs2 errors in the boot log (as shown below) and the QSPI doesn't persist data after reboots.
Code Select
Run /init as init process
INIT: version 2.97 booting
random: fast init done
jffs2: jffs2_scan_dirent_node(): Node CRC failed on node at 0x001d00f0: Read 0x5c97f158, calculated 0xbd247889
jffs2: jffs2_scan_dirent_node(): Node CRC failed on node at 0x001d10cc: Read 0x385250f9, calculated 0x99a1e049
jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x001f0000: 0x19ff instead
jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x001f0004: 0x000c instead
jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x001f0008: 0xb0b1 instead
jffs2: notice: (66) jffs2_get_inode_nodes: Node header CRC failed at 0x1d2ccc. {19ff,e001,00000034,755c292f}
jffs2: notice: (66) jffs2_get_inode_nodes: Node header CRC failed at 0x1d295c. {196b,e001,00000034,755c292f}
jffs2: notice: (66) jffs2_get_inode_nodes: Node header CRC failed at 0x1d2604. {1973,e001,00000032,503776f3}
Starting udev
jffs2: notice: (68) jffs2_get_inode_nodes: Node header CRC failed at 0x1d2ba4. {1954,e002,00000044,98f7fb1d}
jffs2: notice: (68) jffs2_get_inode_nodes: Node header CRC failed at 0x1d2b48. {19be,e002,0000005a,2831dbb1}
jffs2: notice: (68) jffs2_get_inode_nodes: Node header CRC failed at 0x1d2b04. {1916,e002,00000044,98f7fb1d}
jffs2: notice: (68) jffs2_get_inode_nodes: Node header CRC failed at 0x1d2aa8. {19bd,e002,0000005a,2831dbb1}
jffs2: notice: (68) jffs2_get_inode_nodes: Node header CRC failed at 0x1d271c. {1916,e002,00000044,98f7fb1d}
jffs2: notice: (68) jffs2_get_inode_nodes: Node header CRC failed at 0x1d26cc. {1900,e002,0000004f,4ff67c1c}
jffs2: notice: (68) jffs2_get_inode_nodes: Node header CRC failed at 0x1d2688. {190b,e002,00000044,98f7fb1d}
udevd[79]: starting version 3.2.9
jffs2: notice: (68) jffs2_get_inode_nodes: Node header CRC failed at 0x1d2638. {1900,e002,0000004f,4ff67c1c}
random: udevd: uninitialized urandom read (16 bytes read)
jffs2: notice: (68) jffs2_get_inode_nodes: Node header CRC failed at 0x1d25c0. {193e,e002,00000044,98f7fb1d}
random: udevd: uninitialized urandom read (16 bytes read)
jffs2: warning: (68) jffs2_do_read_inode_internal: no data nodes found for ino #66
jffs2: Returned error for crccheck of ino #66. Expect badness...
random: udevd: uninitialized urandom read (16 bytes read)
udevd[80]: starting eudev-3.2.9
jffs2: notice: (68) jffs2_get_inode_nodes: Node header CRC failed at 0x1d2904. {193e,e002,00000057,da5b036c}
jffs2: warning: (68) jffs2_do_read_inode_internal: no data nodes found for ino #70
jffs2: Returned error for crccheck of ino #70. Expect badness...
jffs2: notice: (68) jffs2_get_inode_nodes: Node header CRC failed at 0x1d2c74. {1913,e002,00000057,da5b036c}
jffs2: warning: (68) jffs2_do_read_inode_internal: no data nodes found for ino #74
jffs2: Returned error for crccheck of ino #74. Expect badness...
FAT-fs (mmcblk0p1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.
From the log it can be seen that the MTD device is detected and the patches are taking effect. But the data on QSPI doesn't persist after the reboot.
Code Select
spi-nor spi0.0: s25fl256s1 (32768 Kbytes)
2 fixed-partitions partitions found on MTD device spi0.0
Creating 2 MTD partitions on "spi0.0":
0x000000000000-0x000000e00000 : "qspi-boot"
0x000000e00000-0x000001000000 : "qspi-user"
I have attached a full log if it is of interest. Any pointers to fix the issue is greatly appreciated.
#2
Trenz Electronic FPGA Modules / TE0715 and USB RNDIS on petali...
Last post by Swiss222 - April 22, 2024, 10:00:51 AMHello,
I've asked this question on the Xilinx forum first but got no answer there, hope to get some answer here
I'm trying to implement USB RNDIS interface on Petalinux 2022.2, following this tutorial
I don't know if tutorial is outdated, but I wasn't copying modules on the SD card, just ran modprobe on them upon linux boot.
Secondly, I was only able to activate the USB if I used compatible = "usb-nop-xceiv"; instead of the suggested "ulpi-phy", this might be suggested with the commented out lines in the device tree of TE0715 Test Board design?
Lastly, the device is recognized and running iperf3 works in one direction (windows 11 to board) but crashes and blocks the whole petalinux when ran in board to windows. It looks very similiar to the known issue AR-76735, but this issue should be fixed since petalinux 2021 if I'm not mistaken.
If you need any more details I'll be happy to provide them, we bought around 40 of these boards and it would be crucial to get the usb interface running, thanks
I've asked this question on the Xilinx forum first but got no answer there, hope to get some answer here
I'm trying to implement USB RNDIS interface on Petalinux 2022.2, following this tutorial
I don't know if tutorial is outdated, but I wasn't copying modules on the SD card, just ran modprobe on them upon linux boot.
Secondly, I was only able to activate the USB if I used compatible = "usb-nop-xceiv"; instead of the suggested "ulpi-phy", this might be suggested with the commented out lines in the device tree of TE0715 Test Board design?
Lastly, the device is recognized and running iperf3 works in one direction (windows 11 to board) but crashes and blocks the whole petalinux when ran in board to windows. It looks very similiar to the known issue AR-76735, but this issue should be fixed since petalinux 2021 if I'm not mistaken.
If you need any more details I'll be happy to provide them, we bought around 40 of these boards and it would be crucial to get the usb interface running, thanks
#3
Trenz Electronic FPGA Modules / Re: Si5338 TE0713
Last post by JH - April 17, 2024, 08:56:13 AMHi,
sorry for TE0713 we have only older ClockBuilder Desktop project, which is not longer avaliable from Skyworks.
Start with TE0712 project and configure reconfigure outputs to:
I can send you also this older project file, when you write to support@trenz-electronic.de, in case you still need these files. Rework with newer Tool chain is still on our TODO List, but I can't tell you any timeline at the moment.
br
John
sorry for TE0713 we have only older ClockBuilder Desktop project, which is not longer avaliable from Skyworks.
Start with TE0712 project and configure reconfigure outputs to:
Quote/Internal feedback enabled
//Output Clock 0
// Output is off
//Output Clock 1
// Output is off
//Output Clock 2
// Output Frequency (MHz) = 125.000000000
// Mux Selection = IDn
// MultiSynth = 20 (20.0000)
// R = 1
//Output Clock 3
// Output Frequency (MHz) = 200.000000000
// Mux Selection = IDn
// MultiSynth = 12 1/2 (12.5000)
// R = 1
//Driver 0
// Disabled
// Powered off
// Output voltage = 3.30
// Output type = 3.3V LVDS
// Output state when disabled = StopLow
//Driver 1
// Disabled
// Powered off
// Output voltage = 3.30
// Output type = 3.3V LVDS
// Output state when disabled = StopLow
//Driver 2
// Enabled
// Powered on
// Output voltage = 1.80
// Output type = 1.8V LVDS
// Output state when disabled = StopLow
//Driver 3
// Enabled
// Powered on
// Output voltage = 1.80
// Output type = 1.8V LVDS
// Output state when disabled = StopLow
I can send you also this older project file, when you write to support@trenz-electronic.de, in case you still need these files. Rework with newer Tool chain is still on our TODO List, but I can't tell you any timeline at the moment.
br
John
#4
Trenz Electronic FPGA Modules / Re: share a vitis project with...
Last post by JH - April 17, 2024, 08:45:20 AMHi,
I think this can be helpfull for you
https://support.xilinx.com/s/question/0D52E00006hpKoNSAU/how-to-port-a-vitissdk-project-to-another-pc?language=en_US
You can also export workspace and import on other PC.
We use lokal repository and include them into our reference design, so you can use them like AMD-Xilinx example. But there is less documentation from ADM available how you create such a template. We mostly copy some example from the vitis installation and change it like we need. But I think for you is export workspace or maybe GIT solution from the AMD forum link more suitable
br
John
I think this can be helpfull for you
https://support.xilinx.com/s/question/0D52E00006hpKoNSAU/how-to-port-a-vitissdk-project-to-another-pc?language=en_US
You can also export workspace and import on other PC.
We use lokal repository and include them into our reference design, so you can use them like AMD-Xilinx example. But there is less documentation from ADM available how you create such a template. We mostly copy some example from the vitis installation and change it like we need. But I think for you is export workspace or maybe GIT solution from the AMD forum link more suitable
br
John
#5
Trenz Electronic FPGA Modules / Re: simulation in gowin fpga d...
Last post by JH - April 17, 2024, 08:40:27 AMHi,
I think Govin EDA hasn't simulator intergraded.
https://www.gowinsemi.com/en/support/home/
So you must use Third Party simulator like matlab or so.
br
John
I think Govin EDA hasn't simulator intergraded.
https://www.gowinsemi.com/en/support/home/
So you must use Third Party simulator like matlab or so.
br
John
#6
Trenz Electronic FPGA Modules / share a vitis project with 2 P...
Last post by beautycornbread - April 17, 2024, 03:48:21 AMHello,
I have used the share function for version control which was fine.
Now a college has to work with me on the same project but the platform and appl. system project uses (local) absolute paths (e.g. path to sysroot).
Could anybody plaese give me a hint for a good practise or a tutorial to share vitis projects between 2 colleges or PCs?
I have used the share function for version control which was fine.
Now a college has to work with me on the same project but the platform and appl. system project uses (local) absolute paths (e.g. path to sysroot).
Could anybody plaese give me a hint for a good practise or a tutorial to share vitis projects between 2 colleges or PCs?
#7
Trenz Electronic FPGA Modules / Re: imx219 on TE0726
Last post by MA - April 16, 2024, 07:16:15 AMHi,
without knowing the schematic of your imx219, I assume that the LED is connected to pin 12 of the connector. This is connected to a GPIO on the TE0726, which is not used but is pulled up by default. This means that the LED lights up as soon as the FPGA is supplied with power.
Best regards,
Manuela
without knowing the schematic of your imx219, I assume that the LED is connected to pin 12 of the connector. This is connected to a GPIO on the TE0726, which is not used but is pulled up by default. This means that the LED lights up as soon as the FPGA is supplied with power.
Best regards,
Manuela
#8
Trenz Electronic FPGA Modules / simulation in gowin fpga desig...
Last post by fatherlyhurt - April 15, 2024, 10:37:20 AMhello
I want to simulation with gowin fpga designer and write test bench, but There is no simulation option in the tools menu.
How can I simulate with gowin fpga designer?
I want to simulation with gowin fpga designer and write test bench, but There is no simulation option in the tools menu.
How can I simulate with gowin fpga designer?
#9
Trenz Electronic FPGA Modules / imx219 on TE0726
Last post by ramiroflores - April 12, 2024, 11:41:48 AMWhen i test the imx219 on TE0726, I found that there is a led on imx219 and the led is on. I wonder know that is that once the led is on when camera is connected or when the camera is working. If the led is not on, is it indicates that the camera is not worked?
#10
Trenz Electronic FPGA Modules / Re: TE0720 + TE0703 Gadget Ser...
Last post by Swiss222 - April 08, 2024, 02:03:50 PMHi,
Having the same issue with petalinux 2022 and TE0715 (so zynq 7000). I lost so much time before trying out
"compatible = "usb-nop-xceiv";
I am implementing USB RNDIS and I'm now facing new problems, but I can't be certain they aren't related to this compatibility issue with ulpi-phy . I couldn't find any other mention of this except in this thread, really wish this was documented somewhere.
Having the same issue with petalinux 2022 and TE0715 (so zynq 7000). I lost so much time before trying out
"compatible = "usb-nop-xceiv";
I am implementing USB RNDIS and I'm now facing new problems, but I can't be certain they aren't related to this compatibility issue with ulpi-phy . I couldn't find any other mention of this except in this thread, really wish this was documented somewhere.