Hi,
i have some background in using the older ISE/XPS for Spartan 6, but i am new to the Zynq ecosystem, so i would appreciate any input on where to begin with my new design:
Starting from my own user logic, written in VHDL, which captures some input pins and generates data packets (each packet is several bytes of data, but not always the same amount). This data should be written to the DDR memory connected to the Zynq, until a threshold is reached (~1400bytes). Then the Linux System can do some processing on the data and send it to the world using its Ethernet port. Ideally there would be some double-buffering in the DDR memory so the Linux system has some time to process the data.
The documentation i found from Xilinx and on the Internet about this mentioned some components (HP AXI Port, AXI S2MM interface, ..) but the data transfer was always controlled by the Linux system. I would like my user logic to decide when, and how many data bytes to write to DDR memory.
Can someone point me to the Xilinx component/interface I should be using, to make it as easy as possible for my user logic to write to the DDR RAM ?
Hi,
You can use AXI datamover core, connected to HP AXI Port, it will allow you to send data from AXI Stream interface to Zynq DDR Memory by absolute address. If you don't know exact data amount, "Enable Internediate BTT Mode" feature should be set. At Linux side you need some driver which allocate memory buffers for DMA so this buffers will not be relocated and will have constant physical address. This address you will use as parameter for data transfer.
Best regards
Oleksandr Kiyenko
Thank you, I tried the DataMover with the Xilinx included example project and it is what I was looking for.
I have a question regarding how to access the DDR via Zynq: Do you have an impression of the maximum throughput possible this way?
I am focussing a video application with a "slow" data aquisition via FPGA (around 120 pxls x16bit x 200 lines during 10 sec) and later processing though C. An many as images should be stored in RAM and processes the iterative way, so the size of RAM and the possible through put will limit the number of image I can perform tracking on in these 10 secs. The more images the more precise it will be and I am wondering If it is possible to do this in the FPGA which would be great for this app.
Hi Jürgen,
Xilinx report 391.27 MB/sec with 32 bit bus and 100 MHz clock, think that is more than enough for your application.
Best regards
Oleksandr Kiyenko
Hello Oleksandr
thanks for that piece of information.