Hi
I trying to use axi_one_wire_v1 in my project to obtain MAC address from ds2505-e48.
But when I examined the verilog code I found that the search algorithm of 1-wire protocol hasn't been implemented,
I think using this ip could cause conflict on 1-wire.
because there is ds2432 on same line.
Is this True?
Must I add search algorithm to code?
thanks
Hi Razi,
VHDL code for axi_1wire_v1_00_a core implement only low level 1-wire interface. To read IP address you need software implemantation of 1-wire search read and write.
You can found example in reference project GigaBee_XPS14.2-Base/sw_export/eth_test/src/1wire.c
Best regards
Oleksandr Kiyenko
Thanks alot