Hi all
I an using TE0720 only Pl when i run my code i got the error MicroBlaze is under RESET my intterupt is active high and my clk is also active high
did any one have solution please
Hi,
check reset signal of your microblaze instantiation. If you use processor reset IP and automatically detected polarity, than source must define correctly, otherwise it can happens that the tool use the wrong polarity.
br
John
Hi John,
thank for your reply ,the polartity is also active high
Hi,
if SDK say it's microblaze is into reset, i think some polarity is wrong (that's normally the reason for this message).
check all resets and destinations (DCM, MP, Periphery...).
Add VIO core to your design and monitor all reset signal with Vivado HW Manager.
br
John
hi John,
Iam not using PS only PL i am asking if i should and the pin of the rest to the SC
i still not have clear vesion about the board
thank u
Hi,
miroblaze design is in depended for PS or board.
Check all resets from your design with VIO.
PS: in case you use PL only, it's easier to use FPGA only instead of SoC. Without PS initialisation, PS-PL CLK are not available there are also other restrictions if you do this:
https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
br
John
1) if you are not using PS on TE0720 you have no clock unless you supply the clock from the base or use the free running configuration clock of the FPGA
2) you can tie the reset input of the proc_reset IP core to inactive static value, or better connect it to an output of the Xilinx VIO core, then you can toggle the reset from the Vivado analyzer GUI
Dear John,
i add VIO to my design as u mention ,i got this message "Mismatch between the design programmed into the device xc7z020_1 and the probes file" . the probe
i am wondaring if the pins can make this error i s set to rest to AB9 pin with LVCMOS18
LG
SF
Hi,
either you has an other design running or something is with your VIO Reference CLK.
What's the source of this Reference CLK?
br
John
1 VIO output should go ext_reset_in of reset IP Core
2 you SHOULD NOT connect the VIO output to reset some AXI components they way you did
3 mismatch between bit and ltx means that you have other design loaded to FPGA then the one that corresponds to the ltx
hi,
i try your suggression but still the same problem .
the source of VIO Reference CLK is the clk of microblaze
Hi,
I just add the PS to my design all work gd .I think the problem is from the reset of the clock_wiz
i dont konw what can be
did any one have any idee
Hi,
which reference clk did you use for the DCM (clock_wiz)?
br
John
hi John,
the clock's information is in the attachment
What's the source of the input clk???
br
John
is the the clock of microblaze
???
Microblaze has CLK input, not clk output.
If you did not use PS for clk (which is not available, if PS is not configured with FSBL), than you must use some external.
So either you hasn't any CLK or you has some external CLK.
So which CLK reference did you used as base for your design?
br
John
Dear SF,
you should make yourself familiar with the Zynq concepts and Xilinx FPGA internals too.
It is possible to use PL only, but to be able to use PL only, it is in most cases needed to start the PS, and let the PS to generate the clocks for PL. We have tried to say that here.
In your screenshot you have clock wizard configured to take clock 100MHz from external PIN. TE0720 has no clock on any PL pins. So unless you have 100MHz clock source on your baseboard (it is not ony any of our baseboards!) then you have no clock input. And your clock wizard generated IP Block can not give out any clock as input clk is missing.
your options (with TE0720):
1) let the PS to start (FSBL executed) this would give you up to 4 different clock of your selected frequencies
2) use FPGA configuration clock, this is about 66MHz, always available but only usable for special cases where frequency accuracy does not matter
3) supply some external clock from base to some IO pins
Based on what you have described and written so far, we can not figure out where your clock actually is coming from.