process(M_AXI_ACLK) begin if (rising_edge (M_AXI_ACLK)) then if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then axi_awaddr <= (others => '0'); axi_wdata <= C_M_START_DATA_VALUE; elsif (M_AXI_AWREADY = '1' and axi_awvalid = '1' and M_AXI_WREADY = '1' and axi_wvalid = '1') then -- Signals a new write address/ write data is -- available by user logic if myState = 0 then axi_awaddr <= x"40400030"; --std_logic_vector (unsigned(axi_awaddr) + 4); axi_wdata <= x"00000004"; --std_logic_vector (unsigned(axi_awaddr) + 4); myState <= 1; elsif myState = 1 then myState <= 2; axi_wdata <= x"00000000"; --std_logic_vector (unsigned(axi_awaddr) + 4); axi_awaddr <= x"40400030"; --std_logic_vector (unsigned(axi_awaddr) + 4); ; elsif myState = 2 then myState <= 3; axi_wdata <= x"ABCDDCBA"; --std_logic_vector (unsigned(axi_awaddr) + 4); axi_awaddr <= x"03000000"; --std_logic_vector (unsigned(axi_awaddr) + 4); elsif myState = 3 then myState <= 4; axi_wdata <= x"FECBBCEF"; --std_logic_vector (unsigned(axi_awaddr) + 4); axi_awaddr <= x"04000000"; --std_logic_vector (unsigned(axi_awaddr) + 4); elsif myState = 4 then myState <= 5; axi_wdata <= x"00000001"; --std_logic_vector (unsigned(axi_awaddr) + 4); axi_awaddr <= x"40400030"; --std_logic_vector (unsigned(axi_awaddr) + 4); elsif myState = 5 then myState <= 6; axi_wdata <= x"0E000000"; --std_logic_vector (unsigned(axi_awaddr) + 4); axi_awaddr <= x"40400048"; --std_logic_vector (unsigned(axi_awaddr) + 4); elsif myState = 6 then myState <= 7; axi_wdata <= x"00000020"; --std_logic_vector (unsigned(axi_awaddr) + 4); axi_awaddr <= x"40400058"; --std_logic_vector (unsigned(axi_awaddr) + 4); elsif myState = 7 then myState <= 8; axi_wdata <= x"00000004"; --std_logic_vector (unsigned(axi_awaddr) + 4); axi_awaddr <= x"05000000"; --std_logic_vector (unsigned(axi_awaddr) + 4); elsif myState = 8 then -- PATLAK READ BASLANGIC myState <= 9; axi_wdata <= x"00000004"; --std_logic_vector (unsigned(axi_awaddr) + 4); axi_awaddr <= x"40400000"; --std_logic_vector (unsigned(axi_awaddr) + 4); elsif myState = 9 then myState <= 10; axi_wdata <= x"00000000"; --std_logic_vector (unsigned(axi_awaddr) + 4); axi_awaddr <= x"40400000"; --std_logic_vector (unsigned(axi_awaddr) + 4); elsif myState = 10 then myState <= 11; axi_wdata <= x"00000001"; --std_logic_vector (unsigned(axi_awaddr) + 4); axi_awaddr <= x"40400000"; --std_logic_vector (unsigned(axi_awaddr) + 4); elsif myState = 11 then myState <= 12; axi_wdata <= x"11223344"; --std_logic_vector (unsigned(axi_awaddr) + 4); axi_awaddr <= x"0C000000"; --std_logic_vector (unsigned(axi_awaddr) + 4); elsif myState = 12 then myState <= 15; axi_wdata <= x"0E000000"; --std_logic_vector (unsigned(axi_awaddr) + 4); axi_awaddr <= x"40400018"; --std_logic_vector (unsigned(axi_awaddr) + 4); elsif myState = 15 then myState <= 18; axi_wdata <= x"00000020"; --std_logic_vector (unsigned(axi_awaddr) + 4); axi_awaddr <= x"40400028"; --std_logic_vector (unsigned(axi_awaddr) + 4); else axi_wdata <= x"77777777"; --std_logic_vector (unsigned(axi_awaddr) + 4); axi_awaddr <= x"40400000"; --std_logic_vector (unsigned(axi_awaddr) + 4); end if; --axi_awaddr <= x"0D000000"; --std_logic_vector (unsigned(axi_awaddr) + 4); end if; end if; end process;