Using the Te0712 board package I drag the MIG-7 DDR3 controller over to the block diagram to create a correctly configured DDR3 controller for the module. It works great. But I noticed the AXI port is only 32bit.
When I dig deeper it seems that the settings default to 256bit in the wizard. Does the input auto-configure? The problem here is that I attach it to a SmartConnect and it auto defaults to 32bit as well. This creates a major bandwidth problem.
Any suggestions? What is the best way to instantiate the DDR3 on the module / or change the AXI size?
Update:
I ran the wizard on the MIG Controller with all default values (made no changes) other than the AXI bus size.. changed it to 256. That seemed to work.. on the block diagram
But Vitis returned "Processor held in reset". (microblaze)
I switched it back to 32 bit.. and it "updated output products (I'm not sure if it did this the first time) But then returns an error:
[Vivado 12-3563] The Nested sub-design '/home/andrew/Microblaze/Microblaze0712S_2020/Microblaze0712S_2020.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_1/design_1_mig_7series_0_1.xci' can only be generated by its parent sub-design.
To get it to work I have to delete it.. and drag and drop the DDR3 version in the "boards" section for the 0712. That works.. but I'm back at 32bit.
Any suggestions? The wizard does not seem to invert any resets.. nothing else in the design has changed..
Settings of the MIG that seem to fail...
Vivado Project Options:
Target Device : xc7a100t-fgg484
Speed Grade : -2
HDL : verilog
Synthesis Tool : VIVADO
If any of the above options are incorrect, please click on "Cancel", change the CORE Generator Project Options, and restart MIG.
MIG Output Options:
Module Name : design_1_mig_7series_0_2
No of Controllers : 1
Selected Compatible Device(s) : --
FPGA Options:
System Clock Type : Differential
Reference Clock Type : No Buffer
Debug Port : OFF
Internal Vref : disabled
IO Power Reduction : ON
XADC instantiation in MIG : Enabled
Extended FPGA Options:
DCI for DQ,DQS/DQS#,DM : enabled
Internal Termination (HR Banks) : 50 Ohms
/*******************************************************/
/* Controller 0 */
/*******************************************************/
Controller Options :
Memory : DDR3_SDRAM
Interface : AXI
Design Clock Frequency : 2500 ps (400.00 MHz)
Phy to Controller Clock Ratio : 4:1
Input Clock Period : 2499 ps
CLKFBOUT_MULT (PLL) : 2
DIVCLK_DIVIDE (PLL) : 1
VCC_AUX IO : 1.8V
Memory Type : Components
Memory Part : MT41J256m16XX-125
Equivalent Part(s) : --
Data Width : 32
ECC : Disabled
Data Mask : enabled
ORDERING : Normal
AXI Parameters :
Data Width : 128
Arbitration Scheme : RD_PRI_REG
Narrow Burst Support : 0
ID Width : 1
Memory Options:
Burst Length (MR0[1:0]) : 8 - Fixed
Read Burst Type (MR0[3]) : Sequential
CAS Latency (MR0[6:4]) : 6
Output Drive Strength (MR1[5,1]) : RZQ/7
Controller CS option : Enable
Rtt_NOM - ODT (MR1[9,6,2]) : RZQ/4
Rtt_WR - Dynamic ODT (MR2[10:9]) : Dynamic ODT off
Memory Address Mapping : BANK_ROW_COLUMN
Bank Selections:
Bank: 34
Byte Group T0: DQ[0-7]
Byte Group T1: DQ[16-23]
Byte Group T2: DQ[24-31]
Byte Group T3: DQ[8-15]
Bank: 35
Byte Group T0: Address/Ctrl-3
Byte Group T1: Address/Ctrl-0
Byte Group T2: Address/Ctrl-1
Byte Group T3: Address/Ctrl-2
System_Clock:
SignalName: sys_clk_p/n
PadLocation: H4/G4(CC_P/N) Bank: 35
System_Control:
SignalName: sys_rst
PadLocation: No connect Bank: Select Bank
SignalName: init_calib_complete
PadLocation: No connect Bank: Select Bank
SignalName: tg_compare_error
PadLocation: No connect Bank: Select Bank
Sorry for filling up the forum...
I got it working by directly editing the AXI size in the board file "mir.prj". Lesson.. don't use the wizard. Vivado is hard.. :)
Hi,
no problem.
Quote/home/andrew/Microblaze/Microblaze0712S_2020/Microblaze0712S_2020.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_1/design_1_mig_7series_0_1.xci
I didn't see this message before, I found only this forum post:
https://forums.xilinx.com/t5/Design-Methodologies-and/Vivado-12-3563-error-MIG-7-DDR3/td-p/1007038
mig.prj file is from old ISE, Xilinx has used still old ISE MIG generator in the past also in Vivado. I've recognised that MIG Generator style has changed since some Vivado versions, but the old mig.prj was still working, maybe Xilinx has changed now to new IP stile with backward compatibly to use the mig.prj file. Maybe this makes trouble with changing parameters.
But good to hear that you found a solution for you
br
John