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1
Hi,

zynq-7000.dtsi is only one files, petalinux generate device tree from different source file. SD will set in the most cases correctly from Petalinux hdf update.
But please answer some questions, so I can easier help:
  • Which module did you use? (At first I thought UltraScale, because I saw the "mmc0: error -110" message only on this devices), but now you wrote "zynq-7000.dts"
  • Which Vivado/SDK/Petalinux Version? --> 2015.4? found this on on of the console outputs.
  • Did you connect SD0 or SD1 --> (depending from the module one is in the most cases connected to eMMC)
  • Did you use SD Levelshifter to connect SD Card? Most 7 Series Module use 1.8V Bank power and Levelshifter to 3.3V for SD.
  • Did you use our Board Bart files or create PS by yourself? What's your PS Settings for SD and Bank Power?
  • Did you try another SD Card (slower Speed Class (ex. 4) and only SD2.0 supported --> they works on the T0808 modules without "no-1-8-v;" device tree entry )
br
John


2
Hey John,
Many thanks for the help... but still not able to get SD 0 working.

I updated my stystem-top.dts to include your suggestion and rebuilt the petallinux project and reloaded both image.ub and boot.bin on device.  ( I didn't do a clean...  but maybe I should have?)
Excerpt of that file looks like this now: (system-top.dts)
&sdhci0 {
   /* clock-frequency = <20000000>; */
   
   /* On the Custom I/O board the SD card is routed thru
      the FPGA fabric, and will only handle a max of 25Mhz
      clock, and is currently configured at 20Mhz, therefore
      restrict the device to the same FPGA configured clock.
      Note: the actual device can handle up to at least 50Mhz. */
   max-frequency = <20000000>; 
};

&sdhci1 {
    // disable-wp;
    no-1-8-v;
 
};

I verified with my FPGA folks that SD 0 is being routed thru the PL.  Just curious if can tell me what those two lines actually do?  Going guess "disable-wp" disables write protect (makes it writable perhaps)?  Not sure what this would do:"no-1-8-v", turns power off perhaps?

In any case the boot sequence looks slightly different but still very similar.  Here is an excerpt around the same time that the SD card should be recognized:
mmc0: error -110 whilst initialising SD card
NET: Registered protocol family 29
can: raw protocol (rev 20120528)
can: broadcast manager protocol (rev 20120528 t)
can: netlink gateway (rev 20130117) max_hops=1
Registering SWP/SWPB emulation handler
/opt/Petalinux/petalinux-v2015.4-final/components/linux-kernel/xlnx-4.0/drivers/rtc/hctosys.c: unable to open rtc devi
ALSA device list:
  No soundcards found.
Freeing unused kernel memory: 10588K (c065d000 - c10b4000)

INIT: version 2.88 booting

mmc0: error -110 whilst initialising SD card
mmc0: error -110 whilst initialising SD card

usb 1-1: new high-speed USB device number 2 using ci_hdrc
mmc0: error -110 whilst initialising SD card
mmc1: MAN_BKOPS_EN bit is not set
mmc1: new high speed MMC card at address 0001
mmcblk0: mmc1:0001 Q2J54A 3.58 GiB
usb-storage 1-1:1.0: USB Mass Storage device detected
mmcblk0boot0: mmc1:0001 Q2J54A partition 1 16.0 MiB
mmcblk0boot1: mmc1:0001 Q2J54A partition 2 16.0 MiB
scsi host0: usb-storage 1-1:1.0
mmcblk0rpmb: mmc1:0001 Q2J54A partition 3 512 KiB
 mmcblk0: p1
Creating /dev/flash/* device nodes

Within the zynq-7000.dtsi file, I see these entries:
      sdhci0: sdhci@e0100000 {
         compatible = "arasan,sdhci-8.9a";
         status = "disabled";
         clock-names = "clk_xin", "clk_ahb";
         clocks = <&clkc 21>, <&clkc 32>;
         interrupt-parent = <&intc>;
         interrupts = <0 24 4>;
         reg = <0xe0100000 0x1000>;
      };

      sdhci1: sdhci@e0101000 {
         compatible = "arasan,sdhci-8.9a";
         status = "disabled";
         clock-names = "clk_xin", "clk_ahb";
         clocks = <&clkc 22>, <&clkc 33>;
         interrupt-parent = <&intc>;
         interrupts = <0 47 4>;
         reg = <0xe0101000 0x1000>;
      };

Wondering if my issue is being cause by this is marked disabled???  It looks the same as my Trenz file so I wouldn't think so but I really have no clue. (pl.dtsi on both platforms is empty)

Any additional recommendations would be most helpful.
Thanks in advance.

3
Hi,
you should add following to the device tree:
Code: [Select]
&sdhci1 {
    // disable-wp;
    no-1-8-v;
 
};

this should help to fix this issue with some SD Cards.

We have include this to our 2017.4 reference design:

br
John
4
On the Trenz carrier board this works fine (both u-boot and kernel can access the SD card).  However, when booting an almost identical kernel build on our custom I/O carrier board we can not access the SD card once the kernel has been booted.  It can however, boot (via U-boot) from the SD card.  Our custom I/O carrier board routes the SD pins through the FPGA.  We saw some documentation about reducing the frequency Tran Speed from 50000000 down to 20000000 (via device tree configuration).  However, we are unsure if that update has produced any actual changes. 
When booting on the Trenz carrier board, we eventually see the following msgs during kernel boot (excerpt):
(on this h/w it works)
===============
can: controller area network core (rev 20120528 abi 9)
NET: Registered protocol family 29
mmc0: new high speed SDHC card at address aaaa
can: raw protocol (rev 20120528)
mmcblk0: mmc0:aaaa SL32G 29.7 GiB
can: broadcast manager protocol (rev 20120528 t)
mmcblk0: p1

However, when booting the kernel on our custom I/O carrier board we see the following msgs at around the same boot sequence (excerpt):
This h/w it doesn't work!
=================
mmc0: error -110 whilst initialising SD card
NET: Registered protocol family 29
can: raw protocol (rev 20120528)
can: broadcast manager protocol (rev 20120528 t)
....
INIT: version 2.88 booting

mmc0: error -110 whilst initialising SD card
mmc0: error -110 whilst initialising SD card

usb 1-1: new high-speed USB device number 2 using ci_hdrc
mmc0: error -110 whilst initialising SD card

I've attached output from a printenv (U-boot) and the kernel boot sequence.
I've also attached the device tree update with the updated transpeed (which didn't help), and a couple of the linux kernel configs (from the petalinux project):
/subsystems/linux/configs/u-boot/platform-auto.h
/subsystems/linux/configs/u-boot/platform-top.h

Any help on getting our SD card working within the kernel on our carrier I/O card would be most appreciated!

5
Yes,
if PS is not needed pure FPGA board is a better choice.

If you start with ZynqBerry,  use our reference design at first. I will try to create a first 2017.4 design with wiki description a little earlier.

br
John
6
I see, thank you. I will do these simple examples on a simpler board (without a PS) then and possibly come back to this board later! :)
7
Hi,
on normal design flow yes. For example Zynq PS is need to load programming file from flash. There are much ways to start design.

You can do following (easy way but maybe not complete correct way):
  • Create Design with our Board Part (for exampe 2017.1 design or wait for 2017.4)
  • Remove all IPs (only Zynq must be there)
  • Disable PS-PL AXI (On Zynq PS setup)
  • Enable all 4 PS-PL CLKs and set your preferred CLK frequency
  • Generate Design
  • export hdf to SDK
  • generate fsbl and boot.bin
  • configure flash
  • --> on power on PS is initialised by Flash design and you can overwrite PL part with bitfile programming, which used this clks
br
John
8
Thank you for your help. Am I understanding you correctly if I interpret you as saying that this board, with the Zynq chip, is not usable as "plain" FPGA without an ARM core. I.e., I must initialize and configure the ARM core to be able to use the FPGA part of the chip (because there's no clock available otherwise)? For example, here I would like to just build the LED example, not build an AXI4 peripheral (to the ARM core I assume) as the wiki links tells me to do.
9
Trenz Electronic FPGA Modules / Re: TE-0720 TCL - how to Run only PS Application update???
« Last post by JH on January 19, 2018, 09:55:02 AM »
Hi,
we have new 2017.4 reference design with wiki description:
If you do not change the vivado design, you can recreate Boot.bin with SDK. You found some basic notes on the following link:A description of the TE scripts is on:But normally it's only need to create the project with this scripts. Other features of this scripts are optional (scripts are only a automation of some parts of the xilinx recommended design flow).

Other Links to Xilinx Documentation on:br
John




10
Hello,

we have some reference design to start (include board part files for correct PS settings on vivado):
2017.4 reference design is in preparing with wiki documentation instead of instruction on the download page.

You should use Vivado Block Design (in the most cases easier). You can create own Block Design IPs, which can be written in verilog.
You find some xilinx reference on:
Search for UG number and select your Vivado Version on the URL of the document or use Xilinx DocNav.


On Zynq, PS must be initialized to get PS CLKs running. Normally this is done by FSBL. Configure Bitfiles does not initialise PS part.



For XDC: We provide a master pinout Excel Viewer (only Loc constrain)/Generator :We have also Schematics available:
br
John


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