Trenz Electronic GmbH Support Forum

Trenz Electronic Products => Trenz Electronic FPGA Modules => Topic started by: goli12 on November 21, 2017, 12:20:04 AM

Title: Si5338 Default ClockBuilder Configuration for TE0712
Post by: goli12 on November 21, 2017, 12:20:04 AM
Hello,

I have a TE0712 100T that I would like to change the default input and output clock, while leaving others default.
Using the clockbuilder tool, I have configured the input clock to a 100 MHz differential coming from IN1/IN2.
In addition, I want CLK2 to be configured as a 100 MHz clock going to the GTP pins.

For CLK1A and CLK3, I want to keep it as the default 50 MHz clock.

My question is, what are the default settings for CLK1A and CLK3 I should use with the clockbuilder tool?
I have attached screenshots of my current clockbuilder configuration below. Is my current configuration correct?

Regards
Andrew

(https://i.imgur.com/o1vG8Rd.png)
(https://i.imgur.com/rzczNmA.png)
(https://i.imgur.com/AfXoQI4.png)



Title: Re: Si5338 Default ClockBuilder Configuration for TE0712
Post by: JH on November 21, 2017, 08:26:07 AM
Hello,
yes, this looks good.
Defaults settings are also listed on TE0712 TRM:
br
John
Title: Re: Si5338 Default ClockBuilder Configuration for TE0712
Post by: Lalitnut on November 21, 2017, 10:53:25 AM
Thanks for the settings. It helped me a lot.
Title: Re: Si5338 Default ClockBuilder Configuration for TE0712
Post by: goli12 on November 21, 2017, 09:02:17 PM
Thank you for the confirmation John, and you are very welcome Lalitnut.