Hi Everybody,
I want to drive the DSI Channel with a custom (PL)Zynq design but I saw there is a CPLD between Zynq and DSI Connector. The CPLD occupy the DSI LP-Signal. What is the reson behind it?
How to control those Signals from the Zynq(PL)?
Thank you
Hello,
DSI interface signals connected to CPLD and to Zynq bank 35, see schematics page 3.
Best regards
Oleksandr Kiyenko
Hi Oleksandr,
thank you. DSI_XA and DSI_XB are attached to the PL! Thats ok. But the remaing signals are connected to PS!
I am talking about the LP-Signals.
Sorry... Let me put it another way round. Why do you connect the LP-SIgnals to the CPLD and not to the Zynq PL? I just want to understand it :)
Quote from: gtx on September 11, 2017, 02:11:19 PM
Hi Everybody,
I want to drive the DSI Channel with a custom (PL)Zynq design but I saw there is a CPLD between Zynq and DSI Connector. The CPLD occupy the DSI LP-Signal. What is the reson behind it?
How to control those Signals from the Zynq(PL)?
Thank you
all HS signalling should be handled by the FPGA
as we had not enough FPGA I/O to provide LP support for all lanes we added signals to CPLD, to be able to at least signal transition from LP mode to HS mode as some DSI receivers may not wake up at all with HS signalling only.
Ok I see. But HS and LP timing are close related. How to sync them? Via DSI_XA and DSI_XB? Or MIO52 and MIO53 -which means software!