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UltraScale / Re: TE0803 PS GTR PLL lock
« Last post by JH on Today at 08:30:06 AM »
you can use AMD GTR IBERT to check if GTR looks and you get a stable link:

and yes, as long as you not power of the module SI CLK should be no erased when you has configure it with FSBL
UltraScale / Re: TE0807 clock wizard lock failure
« Last post by JH on Today at 08:23:34 AM »
SI5345 of TE0807 is not preprogrammed. You are sure you configured it correctly?
Can you also check if all your power enable are set high on your carrier. GTH power domain can be disabled:
Trenz Electronic FPGA Modules / Re: S7Mini program flash
« Last post by JH on Today at 07:34:27 AM »
you must generate mcs file which includes your bitstream.
you must change boot.scr script and put it on the correct place in the QSPI(use amd default offset or change it on the config)
we have some notes and links to boot.scr usage:
CYC1000 community projects / Re: Spirit Level example design without NIOS
« Last post by allegedcape on September 28, 2023, 10:29:25 AM »
Thanks a lot! this tips is very useful for me.
Trenz Electronic FPGA Modules / Re: TE0726 -ZynqBerry Power Pins
« Last post by Waldi3141 on September 28, 2023, 10:05:24 AM »

power can also be supplied through PIN 2 and 4 of the J8 Header. Electrically the same.

best regards

Trenz Electronic FPGA Modules / TE0726 -ZynqBerry Power Pins
« Last post by zaknahhas on September 27, 2023, 10:24:20 AM »
Hallo all,
in the Wiki and the Manual of the TE0726. it is mentioned that the board could be powered from the J5 with 5v, which I am doing since years.
Is there negative side to power the board from PINS 2 and 4 on the J8 or there is some reason for not doing that ? Electrically they are connected together, but only J5 is mentioned in the provided info.

Thanks in advance
Trenz Electronic FPGA Modules / TEBF0808 / TE0807 SFP+ Ethernet reference design.
« Last post by tom_kean on September 26, 2023, 04:33:16 PM »

I'm trying to make the TE0807/TEBF0808 combination work with Xilinx AXI Ethernet subsystem cores driving the two SFP+ ports with 1000Base-X modules.  Is there an 'official' reference design or device tree for Petalinux which configures all the necessary motherboard resources to use the SFP+ ports (i.e. SI5345 clock chip, I2C expander which drives the SFP+ control/status signals and SFP+ sockets I2C)?

Thanks in advance.
Trenz Electronic FPGA Modules / Re: TE0720_TE0701_Petalinux_boot
« Last post by Neliz on September 26, 2023, 11:56:22 AM »
Just to add on this, my TE0720-03-61C33MA does not contain the eMMC Nand flash memory U15. Not sure if this is an issue.
Trenz Electronic FPGA Modules / Re: Modifying TE0714 to use lower voltage for LVDS
« Last post by Vadim Y on September 26, 2023, 10:00:24 AM »
Hello Martin,

It is indeed possible to change the VCCIO_0 voltage from 3.3V to 1.8V by replacing certain resistors. However, the main problem is that FLASH S25FL127SABMFV10 only works with a supply voltage of 3.3V. To convert, you will also have to change this component to 1.8V compatible.

Please remember that such interference with the operation of the module automatically voids your warranty.

Best regards,
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