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1
EDDP-EDPS Support / Re: How to initialize the EDDP by BTN3
« Last post by Andrei Errapart on Today at 10:06:33 AM »
Hi Jason Bourne,


There are several projects demonstrating working with the EDDP.

Assuming you are trying to open the project in the folder "IIoT-EDDP/HLS/ARTY_Z7_FULL", you have to use Vivado 2017.1 for that. In this project, FOC is implemented as multiple IP core blocks developed in HLS. When writing one of the previous answers, I had Block Design in this project opened for the reference.

For the project in the folder "SDSoC", Vivado SDSoC 2017.1 is required. In this project, FOC is implemented as a single HLS IP core in a SDSoC project. The source for this can be found in the file "foc.cpp". In the block design of the SDSoC project, the internals of this IP core are not visible.

In the folder "Vitis", one can find Xilinx Vitis project. The FOC is again implemented as a single HLS IP core. This project was implemented by our Xilinx partner, thus I have little experience with it. But you can give it a try.

I am not sure if it helps. If you still are having problems, please supply the Vivado version and the project you are trying to open.

If you have further questions, don't hesitate to ask.


Best regards,
Andrei
2
EDDP-EDPS Support / Re: How to initialize the EDDP by BTN3
« Last post by Jason bourne on Today at 03:58:05 AM »
Hi Andrei Errapart,
Thank you for providing me with the document, which broadens my thinking. Unfortunately, I opened the vivado project through the file you provided to view the PL-side design (vivado's block design). I don't know if you didn't provide the Tcl boot file enough to restore the vivado project. I'm looking forward to seeing the design on the PL side.
Yours sincerely,
Jason
3
Trenz Electronic FPGA Modules / Petalinux Build [Errno 32] Broken Pipe
« Last post by DR on December 01, 2022, 05:17:36 PM »
Hello Petalinux Fans,

For several reasons beyond our control :( We are required to use Ubuntu 22.04 or Fedora 36 on our Systems.
For the past few months, I have been struggling to get the test_board project for TE0820 to build under either of these systems.

The first issue I encounter is a change in "c-stack.c" which can be solved by a patch found here:
https://github.com/openwrt/openwrt/issues/9055

I have not been able to come up with a work around for the second issue ...
Just before the build completes, Petalinux stops with this error:
ERROR: Failed to spawn fakeroot worker to run /home/drector/test_board/os/petalinux/components/yocto/layer/core/meta/recipes-core/initscripts/initscripts_1.0.bb:do_install: [Errno 32] Broken Pipe

This is the stock TE0820-test_board_noprebuilt-vivado_2021.2_withoutvivadopatch-build_11_20220128090819.zip
With Vivado 2021.2, Petalinux 2021.2 and either Ubuntu 22.04 or Fedora 36
No changes except the patch for c-stack.c

Searching the web reveals a few others with the same issue, but no solution.
e.g.
https://support.xilinx.com/s/question/0D52E00007Ci8hgSAB/some-problems-on-petalinux-20211-and-ubuntu-2204-for-zcu111-development?language=en

The surprising thing to me is that more people haven't hit this issue yet over the past few months.

Anyone else see this and have a work-around?

Rebuilding the System with Fedora 34 or Ubuntu 20 - it all works fine out of the box.

Thanks for your help.


4
EDDP-EDPS Support / Re: How Xilinx_eddp_mode Change
« Last post by Andrei Errapart on December 01, 2022, 01:54:12 PM »
Hi Jason Bourne,


The easiest way is to trace this signal on the Block Design. For that one just has to do the following:
1) start _create_win_setup.cmd
2) edit design_basic_settings.cmd
3) start vivado_create_project_guimode.cmd

Open Block Design, select the net routed to "control_in" and you'll see that it is connected to WR0 on the component axi_reg32_0. On the Address Editor, you'll see that the address on the AXI bus is 0x43C0_0000. Just add an offset of 0x40 to this address and write a 32-bit value to it. This register matches the register CONTROL_REG in the SDSoC design and performs same functions; see the file "IIoT-EDDP/doc/FOC_SDSoC.pdf".

To see what's in this register, simply read it.

If you have any further questions, don't hesitate to ask.


best regards,
Andrei
5
EDDP-EDPS Support / Re: How to initialize the EDDP by BTN3
« Last post by Andrei Errapart on December 01, 2022, 11:37:49 AM »
Hi Jason Bourne,


This version of EDDP control code is also running on a CPU, but it might be easier to understand than the Linux one. Please find it attached to this post.


best regards,
Andrei
6
EDDP-EDPS Support / Re: How Xilinx_eddp_mode Change
« Last post by Jason bourne on December 01, 2022, 10:17:58 AM »
Hi Andrei Errapart,
1. There is something wrong with the description in question 1, I want to express that there is a control_in pin in the IP core foc_control_v1.0 (this IP core is found on github), I want to know how the input value of this pin changes;
2. Regarding the second point, thank you for the solution you provided. I will try it after class.
Yours sincerely,
Jason
7
EDDP-EDPS Support / Re: How to initialize the EDDP by BTN3
« Last post by Jason bourne on December 01, 2022, 09:58:23 AM »
At the same time, I hope you can provide the project of implementing FOC only through FPGA, because I am a student who only learns FPGA, and I have not learned Linux embedded, so I feel very confused when I look at the code, I hope you can provide the implementation of vivado. :'(
Yours sincerely,
Jason
8
EDDP-EDPS Support / Re: How to initialize the EDDP by BTN3
« Last post by Jason bourne on December 01, 2022, 09:51:45 AM »
Sir, thank you very much for taking time out of your busy schedule to reply me. Now I have realized the initialization of FOC by my own way. I first guided the motor to rotate through a virtual electrical Angle to find the place where I of the encoder is located. Then, by setting the electrical Angle to 0, electrode A is found and the Angle deviation is calculated. :-*
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EDDP-EDPS Support / Re: How to initialize the EDDP by BTN3
« Last post by Andrei Errapart on November 30, 2022, 12:43:07 PM »
Hi Jason Bourne,


By now it is definitely too late.

In this program, the motor initialization code is a copy of the one found in "focserver".

You can send me a message to request the sources. There is nothing new when compared to the "focserver".


best regards,
Andrei
10
EDDP-EDPS Support / Re: How Xilinx_eddp_mode Change
« Last post by Andrei Errapart on November 30, 2022, 11:42:48 AM »
Hi Jason Bourne,


My apologies for the late answer; for some reason I didn't get notification emails anymore.

1.
I am not really sure as what do you mean by "where the mode in FOC_IP core is inserted". The source code for the FOC HLS can be found in "IIoT-EDDP\Vitis\app_arty_7z_10\src\foc.cpp"; in the function "foc" you can see search for "Mode" to see how it is used.

When you have booted to Linux, you can use the program "focserver" to write to any register as follows:
focserver -w Mode=1
to set mode to 1, e.g. MODE_SPEED as described in the file "foc.h".

This command effectively performs masked write to the the control register. One can manually write to the control register, too. This is the first register (offset 0). Run "lsuio" to see the UIO devices, one of them is either "foc" or "xlnx,foc-". There you get the physical address of the register block. Important: parameter registers start at offset 0x40, status registers start at offset 0x80. On the Linux command line, you can use "devmem" to read and write to this address (offset by 0x40).

2. Regarding the initialization sequence, you can see one in the file "IIoT-EDDP\focserver\files\src\FocDevice.cpp", method "startMotor". When the motor was stopped before setting mode other than stopped, it runs encoder offset search routine at low motor speed by searching for the encoder reading at the moment when current in coil "A" crosses zero point. There is a small offset added, which might vary when you are using a different motor or a different encoder.

Hopefully this helps. If you have any questions, don't hesitate to ask.


best regards,
Andrei
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