Hello I'm working with TE0713 for a video application that is very optimal about ram bandwidth utilization. In my design I need of a total bandwidth of 2970 MByte = 23760 Mbit to read from and write to DDR3 IM4G16D3FABG-125I. Looking at DDR3 datasheet is possible to clock RAM until 800MHz and so clocking ram with 400 MHz give a peack bandwidth of 2*400000000*32 = 25600 Mbit. Looking at mig for artix 7 it seems that max input frequency is 400MHz. Is there a way to achieve the bandwith? Eventually also bypassing MIG and using custom logic to communicate with ram. FPGA and DDR3 can support this frequencies. Thank you.
Hello,
speed limit is given by the FPGA type and IO interface, on Artix it's 800Mb/s for DDR and the most speed grade, you can archive 1066 with speed grade -3 (but this is not so much more), see:
- https://www.xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf
You must switch to a Kintex or Virtex FPGA to archive higher speed.
br
John