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Ethernet does not work correctly on QSPI flash program in TE0729

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david.sakharov:
Hi
im using te0729 with its carrier board teb729 on my project
i design my project hardware in vivado 2019.1 with some change in prebuilt project in te0729 refernce design and export it to sdk.
i implement bsp with lwIP and run my standalone application on sdk debugger.
everything works fine.all 3 Ethernet and other peripherals works correctly.
but
when i program qspi flash with my application and boot from it,the axi-ethernetlite modules doesn't work correctly.it stack on setup-netif(); functions and application doesn't go any further.
i create my fsbl project and enable its debuge info.when i check the fsbl debugger it shows it run correctly and my application run after boot sequence.i also checked ps7-init and ps7-post-config are run in fsbl sequence
i dont know what else to do.
ill be thankful for the helps
best regards

JH:
Hi,
did you built elf as debug or as release in your Boot.bin version?
Maybe you should also write one time to Xilinx forum, this looks like an lwIP stack problem and Xilinx community is much bigger.

br
John

david.sakharov:
hi john, thanks for the reply
i did run my application in both debug and release version,both works fine in sdk debugger.
and i use both of them on my .bin file,none of them didn't work.
and about lwip ,i dont think so it will bug in lwip because it work in debugger runs.
best
david

JH:
Hi,

--- Quote ---and i use both of them on my .bin file,none of them didn't work.
--- End quote ---
did you generate the FSBL also from this vitis project with from the same xsa file?


--- Quote ---and about lwip ,i dont think so it will bug in lwip because it work in debugger runs.
--- End quote ---
that's the big question...why it should be some other bug?
I've seen this from time to time on Xilinx software(for example QSPI programming on native FPGA). Initialisation differs something between the different boot modes. Maybe Lwip expect PHY in another state and fsbl and script version will configure PHY differently or the point of time where your application starts after initialisation and get access to phy differs....

I think you should also ask on Xilinx forum, maybe somebody else has the same issue with LWIP and can give you some hints. I use only Linux...so I can't help much with LWIP

br
John

david.sakharov:
hi jonh

--- Quote from: JH on January 21, 2022, 02:17:02 PM ---Hi,did you generate the FSBL also from this vitis project with from the same xsa file?

--- End quote ---
i generate FSBL with same xsa file for both of them .i did it in sdk 2019.1 .
i also test the fsbl file from the trenz te0729 reference design with my project,it doesnt work ether.

--- Quote from: JH on January 21, 2022, 02:17:02 PM ---I've seen this from time to time on Xilinx software(for example QSPI programming on native FPGA). Initialization differs something between the different boot modes. Maybe Lwip expect PHY in another state and fsbl and script version will configure PHY differently or the point of time where your application starts after initialization and get access to phy differs....

--- End quote ---
i am agree too.because i did some changes in lwip source file (x_topology_c.c) so i can work with all 3 ethernet at same time.
i have to ask them too.
but i have a question.
when i configure a run for my project,it says that it do the following sequence:
1.program fpga
2.run ps7_int
3.run ps7_post_config
4.rum my application
but i check fsbl project,it run ps7_post_config when it want to handoff to application,
thats my question do you think would it be the problem?
meanwhile i change the fsbl to run ps7_post_config  before application,it didnt work.
Regards
david

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